/* Date Stamp: 8/23/2014 */

#ifndef IIO_DFX_h
#define IIO_DFX_h

#include "DataTypes.h"

/* Device and Function specifications:                                        */
/* For all target CPUs:                                                       */
/* IIO_DFX_DEV 6                                                              */
/* IIO_DFX_FUN 3                                                              */

/* VID_IIO_DFX_REG supported on:                                              */
/*       IVT_EP (0x20033000)                                                  */
/*       IVT_EX (0x20033000)                                                  */
/*       HSX (0x20033000)                                                     */
/*       BDX (0x20033000)                                                     */
/* Register default value:              0x8086                                */
#define VID_IIO_DFX_REG 0x12002000
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x000
 */
typedef union {
  struct {
    UINT16 vendor_identification_number : 16;
    /* vendor_identification_number - Bits[15:0], RO, default = 16'b1000000010000110 
       The value is assigned by PCI-SIG to Intel.
     */
  } Bits;
  UINT16 Data;
} VID_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DID_IIO_DFX_REG supported on:                                              */
/*       IVT_EP (0x20033002)                                                  */
/*       IVT_EX (0x20033002)                                                  */
/*       HSX (0x20033002)                                                     */
/*       BDX (0x20033002)                                                     */
/* Register default value on IVT_EP:    0x0E13                                */
/* Register default value on IVT_EX:    0x0E13                                */
/* Register default value on HSX:       0x2F13                                */
/* Register default value on BDX:       0x6F13                                */
#define DID_IIO_DFX_REG 0x12002002
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x002
 */
typedef union {
  struct {
    UINT16 device_identification_number : 16;
    /* device_identification_number - Bits[15:0], RO, default = 16'b0110111100010011 
       Device ID values vary from function to function. Bits 15:8 are equal to 0x6F for 
       the processor. The following list is a breakdown of the function groups. 
       0x6F00 - 0x6F1F : PCI Express and DMI ports
       0x6F20 - 0x6F3F : IO Features (Intel QuickData Technology, APIC, VT, RAS, Intel 
       TXT) 
       0x6F40 - 0x6F5F : Performance Monitors
       0x6F60 - 0x6F7F : DFX
       0x6F80 - 0x6F9F : Intel QPI
       0x6FA0 - 0x6FBF : Home Agent/Memory Controller
       0x6FC0 - 0x6FDF : Power Management
       0x6FE0 - 0x6FFF : Cbo/Ring
       
       Default value may vary based on bus, device, and function of this CSR location.
     */
  } Bits;
  UINT16 Data;
} DID_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PCICMD_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x20033004)                                                  */
/*       IVT_EX (0x20033004)                                                  */
/*       HSX (0x20033004)                                                     */
/*       BDX (0x20033004)                                                     */
/* Register default value:              0x0000                                */
#define PCICMD_IIO_DFX_REG 0x12002004
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x004
 */
typedef union {
  struct {
    UINT16 iose : 1;
    /* iose - Bits[0:0], RO, default = 1'b0 
       1
     */
    UINT16 mse : 1;
    /* mse - Bits[1:1], RO, default = 1'b0 
       1
     */
    UINT16 bme : 1;
    /* bme - Bits[2:2], RO, default = 1'b0 
       1
     */
    UINT16 sce : 1;
    /* sce - Bits[3:3], RO, default = 1'b0 
       1
     */
    UINT16 mwie : 1;
    /* mwie - Bits[4:4], RO, default = 1'b0 
       1
     */
    UINT16 vga_palette_snoop_enable : 1;
    /* vga_palette_snoop_enable - Bits[5:5], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 perre : 1;
    /* perre - Bits[6:6], RW, default = 1'b0 
       1
     */
    UINT16 idsel_stepping_wait_cycle_control : 1;
    /* idsel_stepping_wait_cycle_control - Bits[7:7], RO, default = 1'b0 
       Not applicable to internal devices. Hardwired to 0.
     */
    UINT16 serre : 1;
    /* serre - Bits[8:8], RW, default = 1'b0 
       1
     */
    UINT16 fast_back_to_back_enable : 1;
    /* fast_back_to_back_enable - Bits[9:9], RO, default = 1'b0 
       Not applicable to PCI Express and is hardwired to 0
     */
    UINT16 intx_interrupt_disable : 1;
    /* intx_interrupt_disable - Bits[10:10], RO, default = 1'b0 
       1
     */
    UINT16 rsvd : 5;
    /* rsvd - Bits[15:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} PCICMD_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PCISTS_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x20033006)                                                  */
/*       IVT_EX (0x20033006)                                                  */
/*       HSX (0x20033006)                                                     */
/*       BDX (0x20033006)                                                     */
/* Register default value:              0x0010                                */
#define PCISTS_IIO_DFX_REG 0x12002006
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x006
 */
typedef union {
  struct {
    UINT16 rsvd_0 : 3;
    /* rsvd_0 - Bits[2:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 intxstat : 1;
    /* intxstat - Bits[3:3], RO, default = 1'b0 
       1
     */
    UINT16 capl : 1;
    /* capl - Bits[4:4], RO, default = 1'b1 
       1
     */
    UINT16 pci66mhz_capable : 1;
    /* pci66mhz_capable - Bits[5:5], RO, default = 1'b0 
       Not applicable to PCI Express. Hardwired to 0.
     */
    UINT16 rsvd_6 : 1;
    /* rsvd_6 - Bits[6:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 fb2b : 1;
    /* fb2b - Bits[7:7], RO, default = 1'b0 
       1
     */
    UINT16 mdpe : 1;
    /* mdpe - Bits[8:8], RO, default = 1'b0 
       1
     */
    UINT16 devselt : 2;
    /* devselt - Bits[10:9], RO, default = 2'b00 
       1
     */
    UINT16 sta : 1;
    /* sta - Bits[11:11], RO, default = 1'b0 
       1
     */
    UINT16 rta : 1;
    /* rta - Bits[12:12], RO, default = 1'b0 
       1
     */
    UINT16 rma : 1;
    /* rma - Bits[13:13], RO, default = 1'b0 
       1
     */
    UINT16 sse : 1;
    /* sse - Bits[14:14], RO, default = 1'b0 
       1
     */
    UINT16 dpe : 1;
    /* dpe - Bits[15:15], RO, default = 1'b0 
       1
     */
  } Bits;
  UINT16 Data;
} PCISTS_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RID_IIO_DFX_REG supported on:                                              */
/*       IVT_EP (0x10033008)                                                  */
/*       IVT_EX (0x10033008)                                                  */
/*       HSX (0x10033008)                                                     */
/*       BDX (0x10033008)                                                     */
/* Register default value:              0x00                                  */
#define RID_IIO_DFX_REG 0x12001008
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * "PCIe header Revision ID register"
 */
typedef union {
  struct {
    UINT8 revision_id : 8;
    /* revision_id - Bits[7:0], ROS_V, default = 8'b00000000 
       Reflects the Uncore Revision ID after reset.
       Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID 
       register in the processor uncore. 
       
     */
  } Bits;
  UINT8 Data;
} RID_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CCR_N0_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x10033009)                                                  */
/*       IVT_EX (0x10033009)                                                  */
/*       HSX (0x10033009)                                                     */
/*       BDX (0x10033009)                                                     */
/* Register default value:              0x00                                  */
#define CCR_N0_IIO_DFX_REG 0x12001009


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.3.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT8 register_level_programming_interface : 8;
    /* register_level_programming_interface - Bits[7:0], RO_V, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} CCR_N0_IIO_DFX_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* CCR_N1_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x2003300A)                                                  */
/*       IVT_EX (0x2003300A)                                                  */
/*       HSX (0x2003300A)                                                     */
/*       BDX (0x2003300A)                                                     */
/* Register default value:              0x0880                                */
#define CCR_N1_IIO_DFX_REG 0x1200200A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * PCIe header ClassCode register
 */
typedef union {
  struct {
    UINT16 sub_class : 8;
    /* sub_class - Bits[7:0], RO_V, default = 8'b10000000 
       The value changes dependent upon the dev/func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h80 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h01. 
                 dev-0x0 through 0x7 (return 0x4, d0f0 return 0x0 under default 
       settings) 
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
    UINT16 base_class : 8;
    /* base_class - Bits[15:8], RO_V, default = 8'b00001000 
       The value changes dependent upon the dev-func accessed. A table of the values 
       can be found in the Class-code tab of the msgch spread-sheet  
          Most dev-func will return 8'h08 for this field except for the following 
       dev-func0,func1,... combinations. The following exceptions will return 8'h11. 
                 dev-0x0 through 0x7 (return 0x6)
       	  dev-0x8 func-2
       	  dev-0x9 func-2
       	  dev-0xA func-2
       	  dev-0xB func-1,2,5,6
       	  dev-0x10 func-1,6
       	  dev-0x12 func-1,5
       	  
     */
  } Bits;
  UINT16 Data;
} CCR_N1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CLSR_IIO_DFX_REG supported on:                                             */
/*       IVT_EP (0x1003300C)                                                  */
/*       IVT_EX (0x1003300C)                                                  */
/*       HSX (0x1003300C)                                                     */
/*       BDX (0x1003300C)                                                     */
/* Register default value:              0x00                                  */
#define CLSR_IIO_DFX_REG 0x1200100C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x00c
 */
typedef union {
  struct {
    UINT8 cacheline_size : 8;
    /* cacheline_size - Bits[7:0], RW, default = 8'b00000000  */
  } Bits;
  UINT8 Data;
} CLSR_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PLAT_IIO_DFX_REG supported on:                                             */
/*       IVT_EP (0x1003300D)                                                  */
/*       IVT_EX (0x1003300D)                                                  */
/*       HSX (0x1003300D)                                                     */
/*       BDX (0x1003300D)                                                     */
/* Register default value:              0x00                                  */
#define PLAT_IIO_DFX_REG 0x1200100D
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x00d
 */
typedef union {
  struct {
    UINT8 primary_latency_timer : 8;
    /* primary_latency_timer - Bits[7:0], RO, default = 8'b00000000 
       Not applicable to PCI-Express. Hardwired to 00h.
     */
  } Bits;
  UINT8 Data;
} PLAT_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* HDR_IIO_DFX_REG supported on:                                              */
/*       IVT_EP (0x1003300E)                                                  */
/*       IVT_EX (0x1003300E)                                                  */
/*       HSX (0x1003300E)                                                     */
/*       BDX (0x1003300E)                                                     */
/* Register default value:              0x80                                  */
#define HDR_IIO_DFX_REG 0x1200100E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x00e
 */
typedef union {
  struct {
    UINT8 configuration_layout : 7;
    /* configuration_layout - Bits[6:0], RO, default = 7'b0000000 
       This field identifies the format of the configuration header layout. It is Type 
       0 for all these devices. The default is 00h, indicating a 'endpoint device'. 
     */
    UINT8 multi_function_device : 1;
    /* multi_function_device - Bits[7:7], RO, default = 1'b1 
       This bit defaults to 1b since all these devices are multi-function
     */
  } Bits;
  UINT8 Data;
} HDR_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* BIST_IIO_DFX_REG supported on:                                             */
/*       IVT_EP (0x1003300F)                                                  */
/*       IVT_EX (0x1003300F)                                                  */
/*       HSX (0x1003300F)                                                     */
/*       BDX (0x1003300F)                                                     */
/* Register default value:              0x00                                  */
#define BIST_IIO_DFX_REG 0x1200100F
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x00f
 */
typedef union {
  struct {
    UINT8 bist_tests : 8;
    /* bist_tests - Bits[7:0], RO, default = 8'b00000000 
       Not supported. Hardwired to 00h
     */
  } Bits;
  UINT8 Data;
} BIST_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* SVID_IIO_DFX_REG supported on:                                             */
/*       IVT_EP (0x2003302C)                                                  */
/*       IVT_EX (0x2003302C)                                                  */
/*       HSX (0x2003302C)                                                     */
/*       BDX (0x2003302C)                                                     */
/* Register default value:              0x8086                                */
#define SVID_IIO_DFX_REG 0x1200202C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x02c
 */
typedef union {
  struct {
    UINT16 subsystem_vendor_identification_number : 16;
    /* subsystem_vendor_identification_number - Bits[15:0], RW_O, default = 16'b1000000010000110 
       The default value specifies Intel but can be set to any value once after reset.
     */
  } Bits;
  UINT16 Data;
} SVID_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* SDID_IIO_DFX_REG supported on:                                             */
/*       IVT_EP (0x2003302E)                                                  */
/*       IVT_EX (0x2003302E)                                                  */
/*       HSX (0x2003302E)                                                     */
/*       BDX (0x2003302E)                                                     */
/* Register default value:              0x0000                                */
#define SDID_IIO_DFX_REG 0x1200202E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x02e
 */
typedef union {
  struct {
    UINT16 subsystem_device_identification_number : 16;
    /* subsystem_device_identification_number - Bits[15:0], RW_O, default = 16'b0000000000000000 
       Assigned by the subsystem vendor to uniquely identify the subsystem
     */
  } Bits;
  UINT16 Data;
} SDID_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CAPPTR_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x10033034)                                                  */
/*       IVT_EX (0x10033034)                                                  */
/*       HSX (0x10033034)                                                     */
/*       BDX (0x10033034)                                                     */
/* Register default value:              0x40                                  */
#define CAPPTR_IIO_DFX_REG 0x12001034
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x034
 */
typedef union {
  struct {
    UINT8 capability_pointer : 8;
    /* capability_pointer - Bits[7:0], RO, default = 8'b01000000 
       Points to the first capability structure for the device which is the PCIe 
       capability. 
     */
  } Bits;
  UINT8 Data;
} CAPPTR_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* INTL_IIO_DFX_REG supported on:                                             */
/*       IVT_EP (0x1003303C)                                                  */
/*       IVT_EX (0x1003303C)                                                  */
/*       HSX (0x1003303C)                                                     */
/*       BDX (0x1003303C)                                                     */
/* Register default value:              0x00                                  */
#define INTL_IIO_DFX_REG 0x1200103C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x03c
 */
typedef union {
  struct {
    UINT8 interrupt_line : 8;
    /* interrupt_line - Bits[7:0], RO, default = 8'b00000000 
       N/A for these devices
     */
  } Bits;
  UINT8 Data;
} INTL_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* INTPIN_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x1003303D)                                                  */
/*       IVT_EX (0x1003303D)                                                  */
/*       HSX (0x1003303D)                                                     */
/*       BDX (0x1003303D)                                                     */
/* Register default value:              0x00                                  */
#define INTPIN_IIO_DFX_REG 0x1200103D
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x03d
 */
typedef union {
  struct {
    UINT8 interrupt_pin : 8;
    /* interrupt_pin - Bits[7:0], RO, default = 8'b00000000 
       N/A since these devices do not generate any interrupt on their own
     */
  } Bits;
  UINT8 Data;
} INTPIN_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* MINGNT_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x1003303E)                                                  */
/*       IVT_EX (0x1003303E)                                                  */
/*       HSX (0x1003303E)                                                     */
/*       BDX (0x1003303E)                                                     */
/* Register default value:              0x00                                  */
#define MINGNT_IIO_DFX_REG 0x1200103E
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x03e
 */
typedef union {
  struct {
    UINT8 mgv : 8;
    /* mgv - Bits[7:0], RO, default = 8'b00000000 
       The Device does not burst as a PCI compliant master.
     */
  } Bits;
  UINT8 Data;
} MINGNT_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* MAXLAT_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x1003303F)                                                  */
/*       IVT_EX (0x1003303F)                                                  */
/*       HSX (0x1003303F)                                                     */
/*       BDX (0x1003303F)                                                     */
/* Register default value:              0x00                                  */
#define MAXLAT_IIO_DFX_REG 0x1200103F
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x03f
 */
typedef union {
  struct {
    UINT8 mlv : 8;
    /* mlv - Bits[7:0], RO, default = 8'b00000000 
       The Device has no specific requirements for how often it needs to access the PCI 
       bus. 
     */
  } Bits;
  UINT8 Data;
} MAXLAT_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PXPCAP_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x40033040)                                                  */
/*       IVT_EX (0x40033040)                                                  */
/*       HSX (0x40033040)                                                     */
/*       BDX (0x40033040)                                                     */
/* Register default value:              0x00920010                            */
#define PXPCAP_IIO_DFX_REG 0x12004040
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x040
 */
typedef union {
  struct {
    UINT32 capability_id : 8;
    /* capability_id - Bits[7:0], RO, default = 8'b00010000 
       Provides the PCI Express capability ID assigned by PCI-SIG.
     */
    UINT32 next_ptr : 8;
    /* next_ptr - Bits[15:8], RO, default = 8'b00000000 
       Pointer to the next capability. Set to 0 to indicate there are no more 
       capability structures. 
     */
    UINT32 capability_version : 4;
    /* capability_version - Bits[19:16], RO, default = 4'b0010 
       PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
       
       Note:
       This capability structure is not compliant with Versions beyond 1.0, since they 
       require additional capability registers to be reserved. The only purpose for 
       this capability structure is to make enhanced configuration space available. 
       Minimizing the size of this structure is accomplished by reporting version 1.0 
       compliancy and reporting that this is an integrated root port device. As such, 
       only three Dwords of configuration space are required for this structure. 
     */
    UINT32 device_port_type : 4;
    /* device_port_type - Bits[23:20], RO, default = 4'b1001 
       Device type is Root Complex Integrated Endpoint
     */
    UINT32 slot_implemented : 1;
    /* slot_implemented - Bits[24:24], RO, default = 1'b0 
       N/A for integrated endpoints
     */
    UINT32 interrupt_message_number : 5;
    /* interrupt_message_number - Bits[29:25], RO, default = 5'b00000 
       N/A for this device
     */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPCAP_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DEVCAP_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x40033044)                                                  */
/*       IVT_EX (0x40033044)                                                  */
/*       HSX (0x40033044)                                                     */
/*       BDX (0x40033044)                                                     */
/* Register default value:              0x00008000                            */
#define DEVCAP_IIO_DFX_REG 0x12004044
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x044
 */
typedef union {
  struct {
    UINT32 max_payload_size_supported : 3;
    /* max_payload_size_supported - Bits[2:0], RO, default = 3'b000  */
    UINT32 phantom_functions_supported : 2;
    /* phantom_functions_supported - Bits[4:3], RO, default = 2'b00  */
    UINT32 extended_tag_field_supported : 1;
    /* extended_tag_field_supported - Bits[5:5], RO, default = 1'b0  */
    UINT32 endpoint_l0s_acceptable_latency : 3;
    /* endpoint_l0s_acceptable_latency - Bits[8:6], RO, default = 3'b000  */
    UINT32 endpoint_l1_acceptable_latency : 3;
    /* endpoint_l1_acceptable_latency - Bits[11:9], RO, default = 3'b000  */
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[12:12], RO, default = 1'b0  */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[13:13], RO, default = 1'b0  */
    UINT32 power_indicator_present_on_device : 1;
    /* power_indicator_present_on_device - Bits[14:14], RO, default = 1'b0  */
    UINT32 role_based_error_reporting : 1;
    /* role_based_error_reporting - Bits[15:15], RO, default = 1'b1  */
    UINT32 rsvd_16 : 2;
    /* rsvd_16 - Bits[17:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 captured_slot_power_limit_value : 8;
    /* captured_slot_power_limit_value - Bits[25:18], RO, default = 8'b00000000  */
    UINT32 captured_slot_power_limit_scale : 2;
    /* captured_slot_power_limit_scale - Bits[27:26], RO, default = 2'b00  */
    UINT32 rsvd_28 : 4;
    /* rsvd_28 - Bits[31:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DEVCAP_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DEVCON_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x20033048)                                                  */
/*       IVT_EX (0x20033048)                                                  */
/*       HSX (0x20033048)                                                     */
/*       BDX (0x20033048)                                                     */
/* Register default value:              0x0000                                */
#define DEVCON_IIO_DFX_REG 0x12002048
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * The PCI Express Device Control register controls PCI Express specific 
 * capabilities parameters associated with the device. 
 */
typedef union {
  struct {
    UINT16 correctable_error_reporting_enable : 1;
    /* correctable_error_reporting_enable - Bits[0:0], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 non_fatal_error_reporting_enable : 1;
    /* non_fatal_error_reporting_enable - Bits[1:1], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 fatal_error_reporting_enable : 1;
    /* fatal_error_reporting_enable - Bits[2:2], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 unsupported_request_reporting_enable : 1;
    /* unsupported_request_reporting_enable - Bits[3:3], RO, default = 1'b0 
       N/A for CB DMA
     */
    UINT16 enable_relaxed_ordering : 1;
    /* enable_relaxed_ordering - Bits[4:4], RO, default = 1'b0 
       For most parts, writes from CB DMA are relaxed ordered, except for DMA 
       completion writes. But the fact that CB DMA writes are relaxed ordered is not 
       very useful except when the writes are also non-snooped. If the writes are 
       snooped, relaxed ordering does not provide any particular advantage based on IIO 
       uArch. But when writes are non-snooped, relaxed ordering is required to get good 
       BW and this bit is expected to be set. If this bit is clear, NS writes will get 
       very poor performance. 
     */
    UINT16 max_payload_size : 3;
    /* max_payload_size - Bits[7:5], RO, default = 3'b000 
       N/A for CB DMA
     */
    UINT16 extended_tag_field_enable : 1;
    /* extended_tag_field_enable - Bits[8:8], RO, default = 1'b0  */
    UINT16 phantom_functions_enable : 1;
    /* phantom_functions_enable - Bits[9:9], RO, default = 1'b0 
       Not applicable to CB DMA since it never uses phantom functions as a requester.
     */
    UINT16 auxiliary_power_management_enable : 1;
    /* auxiliary_power_management_enable - Bits[10:10], RO, default = 1'b0 
       Not applicable to CB DMA
     */
    UINT16 enable_no_snoop : 1;
    /* enable_no_snoop - Bits[11:11], RO, default = 1'b0 
       For CB DMA, when this bit is clear, all DMA transactions must be snooped. When 
       set, DMA transactions to main memory can utilize No Snoop optimization under the 
       guidance of the device driver. 
     */
    UINT16 max_read_request_size : 3;
    /* max_read_request_size - Bits[14:12], RO, default = 3'b000 
       N/A to CB DMA since it does not issue tx on PCIE
     */
    UINT16 rsvd : 1;
    /* rsvd - Bits[15:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} DEVCON_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DEVSTS_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x2003304A)                                                  */
/*       IVT_EX (0x2003304A)                                                  */
/*       HSX (0x2003304A)                                                     */
/*       BDX (0x2003304A)                                                     */
/* Register default value:              0x0000                                */
#define DEVSTS_IIO_DFX_REG 0x1200204A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x04a
 */
typedef union {
  struct {
    UINT16 correctable_error_detected : 1;
    /* correctable_error_detected - Bits[0:0], RO, default = 1'b0  */
    UINT16 non_fatal_error_detected : 1;
    /* non_fatal_error_detected - Bits[1:1], RO, default = 1'b0  */
    UINT16 fatal_error_detected : 1;
    /* fatal_error_detected - Bits[2:2], RO, default = 1'b0  */
    UINT16 unsupported_request_detected : 1;
    /* unsupported_request_detected - Bits[3:3], RO, default = 1'b0  */
    UINT16 aux_power_detected : 1;
    /* aux_power_detected - Bits[4:4], RO, default = 1'b0  */
    UINT16 transactions_pending : 1;
    /* transactions_pending - Bits[5:5], RO, default = 1'b0  */
    UINT16 rsvd : 10;
    /* rsvd - Bits[15:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} DEVSTS_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* LNKCAP_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x4003304C)                                                  */
/*       IVT_EX (0x4003304C)                                                  */
/*       HSX (0x4003304C)                                                     */
/*       BDX (0x4003304C)                                                     */
/* Register default value:              0x003BF400                            */
#define LNKCAP_IIO_DFX_REG 0x1200404C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x04c
 */
typedef union {
  struct {
    UINT32 link_speeds_supported : 4;
    /* link_speeds_supported - Bits[3:0], RO, default = 4'b0000  */
    UINT32 maximum_link_width : 6;
    /* maximum_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT32 active_state_link_pm_support : 2;
    /* active_state_link_pm_support - Bits[11:10], RO, default = 2'b01  */
    UINT32 l0s_exit_latency : 3;
    /* l0s_exit_latency - Bits[14:12], RO, default = 3'b111  */
    UINT32 l1_exit_latency : 3;
    /* l1_exit_latency - Bits[17:15], RO, default = 3'b111  */
    UINT32 clock_power_management : 1;
    /* clock_power_management - Bits[18:18], RO, default = 1'b0  */
    UINT32 surprise_down_error_reporting_capable : 1;
    /* surprise_down_error_reporting_capable - Bits[19:19], RO, default = 1'b1  */
    UINT32 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[20:20], RO, default = 1'b1  */
    UINT32 link_bandwidth_notification_capability_a : 1;
    /* link_bandwidth_notification_capability_a - Bits[21:21], RO, default = 1'b1  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[23:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 port_number : 8;
    /* port_number - Bits[31:24], RO, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} LNKCAP_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* LNKSTS_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x20033052)                                                  */
/*       IVT_EX (0x20033052)                                                  */
/*       HSX (0x20033052)                                                     */
/*       BDX (0x20033052)                                                     */
/* Register default value:              0x1000                                */
#define LNKSTS_IIO_DFX_REG 0x12002052
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x052
 */
typedef union {
  struct {
    UINT16 current_link_speed : 4;
    /* current_link_speed - Bits[3:0], RO, default = 4'b0000  */
    UINT16 negotiated_link_width : 6;
    /* negotiated_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT16 rsvd : 1;
    /* rsvd - Bits[10:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 link_training : 1;
    /* link_training - Bits[11:11], RO, default = 1'b0  */
    UINT16 slot_clock_configuration : 1;
    /* slot_clock_configuration - Bits[12:12], RO, default = 1'b1  */
    UINT16 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[13:13], RO, default = 1'b0  */
    UINT16 link_bandwidth_management_status_this : 1;
    /* link_bandwidth_management_status_this - Bits[14:14], RO, default = 1'b0  */
    UINT16 link_autonomous_bandwidth_status_this : 1;
    /* link_autonomous_bandwidth_status_this - Bits[15:15], RO, default = 1'b0  */
  } Bits;
  UINT16 Data;
} LNKSTS_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* LNKCAP2_IIO_DFX_REG supported on:                                          */
/*       IVT_EP (0x4003306C)                                                  */
/*       IVT_EX (0x4003306C)                                                  */
/*       HSX (0x4003306C)                                                     */
/*       BDX (0x4003306C)                                                     */
/* Register default value:              0x003BF400                            */
#define LNKCAP2_IIO_DFX_REG 0x1200406C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x06c
 */
typedef union {
  struct {
    UINT32 link_speeds_supported : 4;
    /* link_speeds_supported - Bits[3:0], RO, default = 4'b0000  */
    UINT32 maximum_link_width : 6;
    /* maximum_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT32 active_state_link_pm_support : 2;
    /* active_state_link_pm_support - Bits[11:10], RO, default = 2'b01  */
    UINT32 l0s_exit_latency : 3;
    /* l0s_exit_latency - Bits[14:12], RO, default = 3'b111  */
    UINT32 l1_exit_latency : 3;
    /* l1_exit_latency - Bits[17:15], RO, default = 3'b111  */
    UINT32 clock_power_management : 1;
    /* clock_power_management - Bits[18:18], RO, default = 1'b0  */
    UINT32 surprise_down_error_reporting_capable : 1;
    /* surprise_down_error_reporting_capable - Bits[19:19], RO, default = 1'b1  */
    UINT32 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[20:20], RO, default = 1'b1  */
    UINT32 link_bandwidth_notification_capability_a : 1;
    /* link_bandwidth_notification_capability_a - Bits[21:21], RO, default = 1'b1  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[23:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 port_number : 8;
    /* port_number - Bits[31:24], RO, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} LNKCAP2_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* LNKCON2_OLD_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x20033070)                                                  */
/*       IVT_EX (0x20033070)                                                  */
/*       HSX (0x20033070)                                                     */
/*       BDX (0x20033070)                                                     */
/* Register default value:              0x0000                                */
#define LNKCON2_OLD_IIO_DFX_REG 0x12002070
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x070
 */
typedef union {
  struct {
    UINT16 active_state_link_pm_control : 2;
    /* active_state_link_pm_control - Bits[1:0], RO, default = 2'b00  */
    UINT16 rsvd_2 : 1;
    /* rsvd_2 - Bits[2:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 read_completion_boundary : 1;
    /* read_completion_boundary - Bits[3:3], RO, default = 1'b0  */
    UINT16 link_disable : 1;
    /* link_disable - Bits[4:4], RO, default = 1'b0  */
    UINT16 retrain_link : 1;
    /* retrain_link - Bits[5:5], RO, default = 1'b0  */
    UINT16 common_clock_configuration : 1;
    /* common_clock_configuration - Bits[6:6], RO, default = 1'b0  */
    UINT16 extended_synch : 1;
    /* extended_synch - Bits[7:7], RO, default = 1'b0  */
    UINT16 enable_clock_power_management_na : 1;
    /* enable_clock_power_management_na - Bits[8:8], RO, default = 1'b0  */
    UINT16 hardware_autonomous_width_disable_ioh : 1;
    /* hardware_autonomous_width_disable_ioh - Bits[9:9], RO, default = 1'b0  */
    UINT16 link_bandwidth_management_interrupt_enable : 1;
    /* link_bandwidth_management_interrupt_enable - Bits[10:10], RO, default = 1'b0  */
    UINT16 link_autonomous_bandwidth_interrupt_enable : 1;
    /* link_autonomous_bandwidth_interrupt_enable - Bits[11:11], RO, default = 1'b0  */
    UINT16 rsvd_12 : 4;
    /* rsvd_12 - Bits[15:12], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} LNKCON2_OLD_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* LNKSTS2_IIO_DFX_REG supported on:                                          */
/*       IVT_EP (0x20033072)                                                  */
/*       IVT_EX (0x20033072)                                                  */
/*       HSX (0x20033072)                                                     */
/*       BDX (0x20033072)                                                     */
/* Register default value:              0x1000                                */
#define LNKSTS2_IIO_DFX_REG 0x12002072
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x072
 */
typedef union {
  struct {
    UINT16 current_link_speed : 4;
    /* current_link_speed - Bits[3:0], RO, default = 4'b0000  */
    UINT16 negotiated_link_width : 6;
    /* negotiated_link_width - Bits[9:4], RO, default = 6'b000000  */
    UINT16 rsvd : 1;
    /* rsvd - Bits[10:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 link_training : 1;
    /* link_training - Bits[11:11], RO, default = 1'b0  */
    UINT16 slot_clock_configuration : 1;
    /* slot_clock_configuration - Bits[12:12], RO, default = 1'b1  */
    UINT16 data_link_layer_link_active : 1;
    /* data_link_layer_link_active - Bits[13:13], RO, default = 1'b0  */
    UINT16 link_bandwidth_management_status_this : 1;
    /* link_bandwidth_management_status_this - Bits[14:14], RO, default = 1'b0  */
    UINT16 link_autonomous_bandwidth_status_this : 1;
    /* link_autonomous_bandwidth_status_this - Bits[15:15], RO, default = 1'b0  */
  } Bits;
  UINT16 Data;
} LNKSTS2_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* SLTCAP2_IIO_DFX_REG supported on:                                          */
/*       IVT_EP (0x40033074)                                                  */
/*       IVT_EX (0x40033074)                                                  */
/*       HSX (0x40033074)                                                     */
/*       BDX (0x40033074)                                                     */
/* Register default value:              0x00000000                            */
#define SLTCAP2_IIO_DFX_REG 0x12004074
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x074
 */
typedef union {
  struct {
    UINT32 attention_button_present : 1;
    /* attention_button_present - Bits[0:0], RO, default = 1'b0  */
    UINT32 power_controller_present : 1;
    /* power_controller_present - Bits[1:1], RO, default = 1'b0  */
    UINT32 mrl_sensor_present : 1;
    /* mrl_sensor_present - Bits[2:2], RO, default = 1'b0  */
    UINT32 attention_indicator_present : 1;
    /* attention_indicator_present - Bits[3:3], RO, default = 1'b0  */
    UINT32 power_indicator_present : 1;
    /* power_indicator_present - Bits[4:4], RO, default = 1'b0  */
    UINT32 hotplug_surprise : 1;
    /* hotplug_surprise - Bits[5:5], RO, default = 1'b0  */
    UINT32 hotplug_capable : 1;
    /* hotplug_capable - Bits[6:6], RO, default = 1'b0  */
    UINT32 slot_power_limit_value : 8;
    /* slot_power_limit_value - Bits[14:7], RO, default = 8'b00000000  */
    UINT32 slot_power_limit_scale : 2;
    /* slot_power_limit_scale - Bits[16:15], RO, default = 2'b00  */
    UINT32 electromechanical_interlock_present : 1;
    /* electromechanical_interlock_present - Bits[17:17], RO, default = 1'b0  */
    UINT32 command_complete_not_capable : 1;
    /* command_complete_not_capable - Bits[18:18], RO, default = 1'b0  */
    UINT32 physical_slot_number : 13;
    /* physical_slot_number - Bits[31:19], RO, default = 13'b0000000000000  */
  } Bits;
  UINT32 Data;
} SLTCAP2_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* SLTSTS2_IIO_DFX_REG supported on:                                          */
/*       IVT_EP (0x2003307A)                                                  */
/*       IVT_EX (0x2003307A)                                                  */
/*       HSX (0x2003307A)                                                     */
/*       BDX (0x2003307A)                                                     */
/* Register default value:              0x0000                                */
#define SLTSTS2_IIO_DFX_REG 0x1200207A
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x07a
 */
typedef union {
  struct {
    UINT16 attention_button_pressed : 1;
    /* attention_button_pressed - Bits[0:0], RO, default = 1'b0  */
    UINT16 power_fault_detected : 1;
    /* power_fault_detected - Bits[1:1], RO, default = 1'b0  */
    UINT16 mrl_sensor_changed : 1;
    /* mrl_sensor_changed - Bits[2:2], RO, default = 1'b0  */
    UINT16 presence_detect_changed : 1;
    /* presence_detect_changed - Bits[3:3], RO, default = 1'b0  */
    UINT16 command_completed : 1;
    /* command_completed - Bits[4:4], RO, default = 1'b0  */
    UINT16 mrl_sensor_state : 1;
    /* mrl_sensor_state - Bits[5:5], RO, default = 1'b0  */
    UINT16 presence_detect_state : 1;
    /* presence_detect_state - Bits[6:6], RO, default = 1'b0  */
    UINT16 electromechanical_latch_status : 1;
    /* electromechanical_latch_status - Bits[7:7], RO, default = 1'b0  */
    UINT16 data_link_layer_state_changed : 1;
    /* data_link_layer_state_changed - Bits[8:8], RO, default = 1'b0  */
    UINT16 rsvd : 7;
    /* rsvd - Bits[15:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} SLTSTS2_IIO_DFX_STRUCT;
#endif /* ASM_INC */
















/* REUTENGLTRCON_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x4003311C)                                                  */
/*       IVT_EX (0x4003311C)                                                  */
/*       HSX (0x4003311C)                                                     */
/*       BDX (0x4003311C)                                                     */
/* Register default value:              0x00000000                            */
#define REUTENGLTRCON_IIO_DFX_REG 0x1200411C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * Additional Information on 'Links To Control' Bit Field
 */
typedef union {
  struct {
    UINT32 linkctrl : 16;
    /* linkctrl - Bits[15:0], RWS_L, default = 16'b0000000000000000 
       Link ControlDependency on Link Control is called out explicitly throughout 
       various REUT registers definition when it occurs. 
       
       Every even bit in Link Control represents a Link.
       Bit 0 = Link 0
       Bit 2 = Link 1
       Bit 4 = Link 2
       Etc.
       
       The following Rules apply to the Even bits of Link Control.
       If Can Transmit or Receive on Multiple Links? = 0 then the even Bits of Link 
       Control are not writable and must always be equal to Link Capability. Link 
       Select must be the sole method to determine which Link is being accessed and 
       controlled. 
       If Can Transmit or Receive on Multiple Links? = 1 then the REUT engine can 
       transmit and/or receive on multiple links based on the following rules. 
       If Can Select a Partial Set Of Link Control is set to 0 then the even Bits of 
       Link Control are not writable and must always be equal to Link Capability 
       Else,
       If Can Select a Partial Set Of Link Control is set to 1 then the even bits of 
       Link Control can be set to '0' or '1' for any combination of Links which are set 
       to '1' in the Link Capability. Writing to register dependent on Link Control 
       will cause only the selected Links to be written to while leaving non selected 
       Link register values unchanged. 
       
       Notes:
       Locked by REUTENGLCK
     */
    UINT32 rsvd_16 : 7;
    /* rsvd_16 - Bits[22:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 linkautoneg : 1;
    /* linkautoneg - Bits[23:23], RWS_L, default = 1'b0 
       If Link Auto Configuration Capability is set to 0 then Link Auto Configuration 
       is always reserved as 0. 
       
       Else,
       
       If Link Auto Configuration is set to 0 then all odd Link Control bits that are 
       set to '1' will condition how the Pre Configuration Lane ID values are set. 
       
       If Link Auto Configuration is set to 1 then all odd Link Control bits are 
       ignored and are assumed to be 0. 
       
       See Link Control for more details.
       
       Notes:
       Locked by REUTENGLCK
     */
    UINT32 rsvd_24 : 1;
    /* rsvd_24 - Bits[24:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 linkselect : 2;
    /* linkselect - Bits[26:25], RWS_L, default = 2'b00 
       Link SelectThis bit is used in conjunction with many other REUT register bits 
       which are explicitly called out within the description field of the particular 
       bit where it has a potential affect. 
       
       The bit field selects the following link depending on which REUT engine is being 
       used. 
       00: PXP0, PXP1, PXP3, PXP7
       01: -------, PXP2, PXP4, PXP8
       10: -------, --------, PXP5, PXP9
       11: --------, -------, PXP6, PXP10
       
       Notes:
       Locked by REUTENGLCK
     */
    UINT32 linkselect_notused : 2;
    /* linkselect_notused - Bits[28:27], RWS_L, default = 2'b00  */
    UINT32 rsvd_29 : 3;
    /* rsvd_29 - Bits[31:29], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} REUTENGLTRCON_IIO_DFX_STRUCT;
#endif /* ASM_INC */




/* REUTERRRCV_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x40033124)                                                  */
/*       IVT_EX (0x40033124)                                                  */
/*       HSX (0x40033124)                                                     */
/*       BDX (0x40033124)                                                     */
/* Register default value:              0x00000000                            */
#define REUTERRRCV_IIO_DFX_REG 0x12004124
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * This register is dependent on the value of the link selection CSR: 
 * XPREUT_ENG_LTRCON.LinkSelect[1:0]. 
 */
typedef union {
  struct {
    UINT32 rcverrcount : 15;
    /* rcverrcount - Bits[14:0], RW1CS, default = 15'b000000000000000 
       If # of links supported is greater than 0 there is a Link Select dependence for 
       this field. 
       
       ECC/Receiver Error Counter is used to help measure bit errors while in L0. It is 
       useful to correlate the well controlled stress of Loopback.Pattern tests to 
       normal operating conditions. 
       
       PCI Express Link Behavior:
       The Receiver Error Counter is incremented every time an 8b/10b receiver error 
       (i.e. decode error) is detected. 
       Receiver Error Counter is a direct measure of the physical layer stability and 
       is used in conjunction with CRC Counter and Recovery Counter to monitor L0 
       physical layer behavior. 
       When Receiver Error Counter wraps around the corresponding overflow bit (bit 15) 
       is set to '1'. 
       Cleared only by software or Cold Reset.
     */
    UINT32 rcverroverflow : 1;
    /* rcverroverflow - Bits[15:15], RW1CS, default = 1'b0 
       If # of links supported is greater than 0 there is a Link Select dependence for 
       this field. 
       
       PCI Express Link Behavior:
       The Receiver Error Counter is incremented every time an 8b/10b receiver error 
       (i.e. decode error) is detected. 
       When Receiver Error Counter wraps around the corresponding overflow bit (bit 15) 
       is set to '1'. 
       Cleared only by software or Cold Reset.
     */
    UINT32 reccount : 15;
    /* reccount - Bits[30:16], RW1CS, default = 15'b000000000000000 
       If # of links supported is greater than 0 there is a Link Select dependence for 
       this field. 
       
       ECC Dimm1/Recovery Counter is used to help measure bit errors while in L0. It is 
       useful to correlate the well controlled stress of Loopback.Pattern tests to 
       normal operating conditions. 
       
       PCI Express Link Behavior:
       The Recovery Counter is used to validate successful transitions from L0s to L0 
       as measured by the Recovery counter not being incremented. 
       Recovery is also entered when multiple errors occur on a Link and the protocol 
       layer attempts to Recover stability. 
       The Recovery Counter is incremented every time a Link enters the Recovery LTSSM 
       state. 
       When Recovery Counter wraps around the corresponding overflow bit (bit 31) is 
       set to '1'. 
       Cleared only by software or Cold Reset.
     */
    UINT32 recoverflow : 1;
    /* recoverflow - Bits[31:31], RW1CS, default = 1'b0 
       If # of links supported is greater than 0 there is a Link Select dependence for 
       this field. 
       
       PCI Express Link Behavior:
       When Recovery Counter wraps around the Recovery Overflow bit (bit 31) is set to 
       '1'. 
       Cleared only by software or Cold Reset.
     */
  } Bits;
  UINT32 Data;
} REUTERRRCV_IIO_DFX_STRUCT;
#endif /* ASM_INC */




/* REUTENGLTRON_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x4003312C)                                                  */
/*       IVT_EX (0x4003312C)                                                  */
/*       HSX (0x4003312C)                                                     */
/*       BDX (0x4003312C)                                                     */
/* Register default value:              0x00400020                            */
#define REUTENGLTRON_IIO_DFX_REG 0x1200412C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x12c [Index=reutengltrcon.linkselect]
 */
typedef union {
  struct {
    UINT32 phyreset : 1;
    /* phyreset - Bits[0:0], RW, default = 1'b0 
       Used to Reset the Physical Layer, and is Link Type dependent in it usage and 
       definition. 
       
       PCI Express Behavior:
       
       If # of links supported is greater than 0 then
       Link Select must always be used to display the current read value for this 
       field. 
       
       There is a write dependency for this field based on the value of Can Transmit or 
       Receive on Multiple Links? 
       If Can Transmit or Receive on Multiple Links? = 0 then Link Select must be used 
       to only write to the selected Link. 
       If Can Transmit or Receive on Multiple Links? = 1 then every Link selected in 
       Link Control will receive the written value. 
       
       Physical Layer Reset is RWD type for PCI Express and must be both set and 
       cleared by software. 
       
       Setting Physical Layer Reset to 1 continuously initiates a transition to 
       Detect.Quiet and selected Links must not perform any Detect functions until 
       Physical Layer Reset is cleared and then the LTSSM may proceed with Detect.Quiet 
       as specified in the PCI Express Specification. 
       
       Setting and clearing must be done by software.
       
       Notes:
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 rsvd_1 : 4;
    /* rsvd_1 - Bits[4:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 phyinit : 1;
    /* phyinit - Bits[5:5], RWS, default = 1'b1 
       If # of links supported is greater than 0 then
       Link Select must always be used to display the current read value for this 
       field. 
       
       There is a write dependency for this field based on the value of Can Transmit or 
       Receive on Multiple Links? 
       If Can Transmit or Receive on Multiple Links? = 0 then Link Select must be used 
       to only write to the selected Link. 
       If Can Transmit or Receive on Multiple Links? = 1 then every Link selected in 
       Link Control will receive the written value. 
       
       PCI Express Behavior:
       Writing a 0 to PhyinitBegin stops the LTSSM from entering Detect.Quiet state 
       after any transition to Detect is initiated. 
       The RX impedance must meet ZRX-HIGH-IMP-DC so as to not allow the endpoint to 
       enter compliance. 
       PhyInitBegin can be used to synchronize an HVM tester and DUT, and also freeze 
       any LTSSM at the beginning of initialization to help LTSSM debug. 
       
       0: Stall initialization on default initialization
       1: Begin initialization if stalled on default initialization
       
       Notes:
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 rsvd_6 : 2;
    /* rsvd_6 - Bits[7:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 initmode : 3;
    /* initmode - Bits[10:8], RWS, default = 3'b000 
       If # of links supported is greater than 0 then
       Link Select must always be used to display the current read value for this 
       field. 
       
       There is a write dependency for this field based on the value of Can Transmit or 
       Receive on Multiple Links? 
       If Can Transmit or Receive on Multiple Links? = 0 then Link Select must be used 
       to only write to the selected Link. 
       If Can Transmit or Receive on Multiple Links? = 1 then every Link selected in 
       Link Control will receive the written value. 
       
       Initialization Mode determines how a selected Link Physical Layer will 
       initialize. 
       
       Note: Initialization Mode is a key field that will need to be tied into the 
       implementation of Link initialization and so great care should be taken in 
       making sure these fields are working as designed. 
       
       PCI Express Link Behavior :
       A change in the Initialization Mode only takes effect after Physical Layer Reset 
       is asserted. 
       
       000: Normal Initialization. This is the normal protocol mode for the Link.
       Transmitted TS Bit Encodings - Loopback = 0 and Compliance Receive = 0
       
       001: Initialization towards Loopback state. This is requires some amount of Link 
       functionality to initialize. Details in respective architecture sections. 
       Transmitted TS Bit Encodings - Loopback = 1 and Compliance Receive = 0
       
       010: Tester Mode - Bypass all Detect states and directly enter Polling.Active. 
       Used with Phy Init Begin to sync up test equipment and DUTs. 
       Transmitted TS Bit Encodings - Loopback = 1 and Compliance Receive = 0
       
       011: Initialization towards Loopback.Compliance Master. This is requires Gen1 
       Speed Link functionality to initialize. 
       Transmitted TS Bit Encodings - Loopback = 1 and Compliance Receive = 1
       
       100: Forced Entry to Compliance Master. This is requires limited or no Link 
       functionality to initialize. 
       The transition to Compliance Master immediately follows the clearing of Physical 
       Layer Reset. 
       Transmitted TS Bit Encodings - Loopback = don't care and Compliance Receive = 
       don't care since it never occurs. 
       
       101: Forced Entry to Compliance Slave. This is requires limited or no Link 
       functionality to initialize. 
       The transition to Compliance Slave immediately follows the clearing of Physical 
       Layer Reset. 
       Transmitted TS Bit Encodings - Loopback = don't care and Compliance Receive = 
       don't care since it never occurs. 
       
       110: Initialization towards Compliance Receive (modified pattern 2 in PCI 
       Express 2). This is requires limited Link functionality. 
       Transmitted TS Bit Encodings - Loopback = 0 and Compliance Receive = 1
       
       111: Reserved.
       
       Notes:
       See respective Link architecture chapter for more details.
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 rsvd_11 : 1;
    /* rsvd_11 - Bits[11:11], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 initabortfrz : 1;
    /* initabortfrz - Bits[12:12], RWS, default = 1'b0 
       If # of links supported is greater than 0 then
       Link Select must always be used to display the current read value for this 
       field. 
       
       There is a write dependency for this field based on the value of Can Transmit or 
       Receive on Multiple Links? 
       If Can Transmit or Receive on Multiple Links? = 0 then Link Select must be used 
       to only write to the selected Link. 
       If Can Transmit or Receive on Multiple Links? = 1 then every Link selected in 
       Link Control will receive the written value. 
       
       PCI Express Behavior:
       0: Follow PCI Specification
       1: Freeze the LTSSM state Machine at any point a timeout causes an exit to 
       Detect. This will be used with the RX and TX state tracker to help debug LTSSM 
       problems. 
       
       Notes:
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 disautocompl : 1;
    /* disautocompl - Bits[13:13], RWS, default = 1'b0 
       If # of links supported is greater than 0 then
       Link Select must always be used to display the current read value for this 
       field. 
       
       There is a write dependency for this field based on the value of Can Transmit or 
       Receive on Multiple Links? 
       If Can Transmit or Receive on Multiple Links? = 0 then Link Select must be used 
       to only write to the selected Link. 
       If Can Transmit or Receive on Multiple Links? = 1 then every Link selected in 
       Link Control will receive the written value. 
       
       PCI Express Behavior:
       0: Path from Polling to Compliance because of squelch is allowed.
       1: Path from Polling to Compliance because of squelch is disabled.
       
       Notes:
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 rsvd_14 : 8;
    /* rsvd_14 - Bits[21:14], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 enablescram : 1;
    /* enablescram - Bits[22:22], RWS, default = 1'b1 
       If # of links supported is greater than 0 then
       Link Select must always be used to display the current read value for this 
       field. 
       
       There is a write dependency for this field based on the value of Can Transmit or 
       Receive on Multiple Links? 
       If Can Transmit or Receive on Multiple Links? = 0 then Link Select must be used 
       to only write to the selected Link. 
       If Can Transmit or Receive on Multiple Links? = 1 then every Link selected in 
       Link Control will receive the written value. 
       
       PCI Express Behavior:
       0: Disable L0 data scrambling. The transmitted disable scrambling bit in TS1 
       must be set to equal 1. 
       1: Scramble data in L0. The transmitted disable scrambling bit in TS1 must be 
       set to equal 0. 
       
       Notes:
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 rsvd_23 : 6;
    /* rsvd_23 - Bits[28:23], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 lanesel : 2;
    /* lanesel - Bits[30:29], RWS_L, default = 2'b00 
       Notes:
       Locked by REUTENGLCK
     */
    UINT32 bypassdet : 1;
    /* bypassdet - Bits[31:31], RWS, default = 1'b0 
       If # of links supported is greater than 0 then
       Link Select must always be used to display the current read value for this 
       field. 
       
       There is a write dependency for this field based on the value of Can Transmit or 
       Receive on Multiple Links? 
       If Can Transmit or Receive on Multiple Links? = 0 then Link Select must be used 
       to only write to the selected Link. 
       If Can Transmit or Receive on Multiple Links? = 1 then every Link selected in 
       Link Control will receive the written value. 
       
       Notes:
       Bypass Detect will assume that all active Lanes that aren't disabled by TX Data 
       Lane Disable Detect a termination and immediately move into Polling.Active 
       anytime a transition to Detect is made. 
       Bypass Detect can be utilized with Phy Init Begin to sync a DUT with an HVM 
       tester to enter Polling.Active at approximately the same time. 
       Link will stay in detect as long the spec states and then move to 
       Polling.Active. This is used to bypass the receive detect state for debug 
       issues. 
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
  } Bits;
  UINT32 Data;
} REUTENGLTRON_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* REUTPHTDC_IIO_DFX_REG supported on:                                        */
/*       IVT_EP (0x40033130)                                                  */
/*       IVT_EX (0x40033130)                                                  */
/*       HSX (0x40033130)                                                     */
/*       BDX (0x40033130)                                                     */
/* Register default value:              0x00000000                            */
#define REUTPHTDC_IIO_DFX_REG 0x12004130


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x130
 */
typedef union {
  struct {
    UINT32 txdatalanedis : 16;
    /* txdatalanedis - Bits[15:0], RWS_L, default = 16'b0000000000000000 
       A bit mask used for selectively enabling/disabling data TX Lanes.
       
       A bit value of 1 indicates the corresponding lane is disabled.
       Each bit represents a unique Lane independent of pre or post Link Configuration. 
       The number of bits in this field vary, depending on the number of lanes in this 
       link. The valid number of lanes will be 4, 8, or 16. For links with less than 16 
       lanes, the remaining bits will be reserved. 
       
       Bit 0: Controls Lane 0.
       Bit 1: Controls Lane 1.
       .. and so on.
       
       Notes:
       This register is not Link Select dependent.
       Used for debug and validation purposes.
       Locked by REUTENGLCK
     */
    UINT32 rsvd : 15;
    /* rsvd - Bits[30:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 csr_tdc_dont_maskrxdet4tdc : 1;
    /* csr_tdc_dont_maskrxdet4tdc - Bits[31:31], RWS_L, default = 1'b0 
       For TDC control, ignore tx detection. IVT 3247662.
       Used for debug and validation purposes.
       Locked by REUTENGLCK
     */
  } Bits;
  UINT32 Data;
} REUTPHTDC_IIO_DFX_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */










/* REUTPHPIS_IIO_DFX_REG supported on:                                        */
/*       IVT_EP (0x40033140)                                                  */
/*       IVT_EX (0x40033140)                                                  */
/*       HSX (0x40033140)                                                     */
/*       BDX (0x40033140)                                                     */
/* Register default value:              0x00000000                            */
#define REUTPHPIS_IIO_DFX_REG 0x12004140
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * This register is dependent on the value of the link selection CSR: 
 * XPREUT_ENG_LTRCON.LinkSelect[1:0].REUT_PH_XP Tracking State Table 
 */
typedef union {
  struct {
    UINT32 linkup : 1;
    /* linkup - Bits[0:0], RO_V, default = 1'b0 
       If # of links supported is greater than 0 then the behavior of this register is 
       Link Select dependent. 
       
       PCI Express Behavior:
       Set to 0 as dictated by the PCI Base Specification when entering Detect, L1, 
       Loopback, or Hot Reset. 
       Set to 1 when entering L0.
     */
    UINT32 rsvd_1 : 7;
    /* rsvd_1 - Bits[7:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 ltssmstate : 5;
    /* ltssmstate - Bits[12:8], RO_V, default = 5'b00000 
       If # of links supported is greater than 0 then the behavior of this register is 
       Link Select dependent. 
       
       PCI Express Link Behavior:
       Indicates the current state of the remaining Lanes in the TX LTSSM and has no 
       Lane dependency. 
       
       Note: Since we do not have separate Rx and Tx LTSSMs, the Tx tracker indicates 
       the state of the LTSSM and the Rx tracker will have lane specific debug 
       information regarding the LTSSM. 
       
       Rx tracker: lane specific receive state information
       Tx tracker: LTSSM state information of the link.
       State tracker encoding is given in Table 14-62.
     */
    UINT32 rsvd_13 : 3;
    /* rsvd_13 - Bits[15:13], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rxtracker : 4;
    /* rxtracker - Bits[19:16], RO_V, default = 4'b0000 
       If # of links supported is greater than 0 then the behavior of this register is 
       Link Select dependent. 
       
       PCI Express Behavior:
       Displays the current Lane status.
       The displayed Lane status is dependent on the value RX Error Lane Select field
       
       The decoding for the various Lane Status states is the following:
       0000: lane didn't do rcv detect or discarded during training.
       0001: lane did rcv detect
       0010: lane did rcv detect and exit EI seen
       0011: COM decoded
       0100: rcvd TS1
       0101: rcvd multiple TSs
       0110: rcvd 2 TS with link num
       0111: reserved
       1001: RCVD TS with lane num set
       1010: lane configured (entered cfg idle)
       1011: rcvd polarity inverted TS1
       1100: RCV_TS_2NPAD
       1101: deconfigure lane in cfg complete send EIOS
       1110: deconfigure lane in cfg complete
       1111: SEND EIOS on lane
       
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 rsvd_20 : 8;
    /* rsvd_20 - Bits[27:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 testbusy : 1;
    /* testbusy - Bits[28:28], RO_V, default = 1'b0 
       If # of links supported is greater than 0 then the behavior of this register is 
       Link Select dependent. 
       
       PCI Express Behavior
       This bit indicates a test in progress, or failure to obtain Loopback.Marker 
       training sequences while in Loopback.Marker state 
       Set in Loopack.Pattern, or when first entering Loopback.Marker from Config or 
       Recovery States 
       Cleared either in Loopback.Marker when receiving a Loopback.Marker training 
       sequence, or by entering Detect. 
       TestBusy is polled while in Loopback. When it is equal to 0 the user should know 
       that any previous Loopback test has completed, and that a new test is ready to 
       be initiated using Start Test. 
       
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 globerr : 1;
    /* globerr - Bits[29:29], RO_V, default = 1'b0 
       Useful only when the # of links supported is greater than 0 otherwise Global 
       Error is always set to 0. 
       
       There is no Link Select dependency for this field
       
       PCI Express Link Behavior:
       Global Error is set upon any error detected on any Link during Loopback.Pattern.
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 globtestbusy : 1;
    /* globtestbusy - Bits[30:30], RO_V, default = 1'b0 
       Useful only when If number of links supported (NumLinks) is greater than 0, 
       otherwise GlobTestBusy is always set to 0. 
       
       GlobTestBusy represents the OR'ing of all the separate Link specific Test Busy 
       bits 
       
       Allows for polling of one bit to determine whether any Link has not successfully 
       re-entered Loopback.Marker from Loopback.Pattern. 
       
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 globteststart : 1;
    /* globteststart - Bits[31:31], RO_V, default = 1'b0 
       Global Start Test represents the or'ing of all the separate Link specific Start 
       Test bits 
       
       Allows for polling of one bit to determine whether any Link has not successfully 
       entered Loopback.Pattern from Loopback.Marker. 
       
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
  } Bits;
  UINT32 Data;
} REUTPHPIS_IIO_DFX_STRUCT;
#endif /* ASM_INC */














































/* REUTPERLANEERR_IIO_DFX_REG supported on:                                   */
/*       BDX (0x400331B8)                                                     */
/* Register default value:              0x00000000                            */
#define REUTPERLANEERR_IIO_DFX_REG 0x120041B8

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * Implements the 8-bit per lane error count, overflow flag.
 */
typedef union {
  struct {
    UINT32 reutperlanecnt : 4;
    /* reutperlanecnt - Bits[3:0], RWS_L, default = 4'b0000 
       Notes:
       Locked by REUTENGLCK
       This selects the Per Lane 8-bit error counter to be read also used for the Burst 
       Mode error counter lane. 
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 rsvd_4 : 4;
    /* rsvd_4 - Bits[7:4], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 reutperlaneerrcnt : 8;
    /* reutperlaneerrcnt - Bits[15:8], RW1CS_L, default = 8'b00000000 
       Notes:
       Locked by REUTENGLCK
       8-bit Per Lane Error counter value, the lane is selected with fields [3:0] in 
       this register as below. 
     */
    UINT32 reutperlaneerrcntovrflw : 1;
    /* reutperlaneerrcntovrflw - Bits[16:16], RW1CS_L, default = 1'b0 
       Notes:
       Locked by REUTENGLCK
       Overflow bit for the 8-bit Per lane error counter.
     */
    UINT32 rsvd_17 : 15;
    /* rsvd_17 - Bits[31:17], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} REUTPERLANEERR_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* REUTPATTES_IIO_DFX_REG supported on:                                       */
/*       BDX (0x400331BC)                                                     */
/* Register default value:              0x00000000                            */
#define REUTPATTES_IIO_DFX_REG 0x120041BC

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * This register is dependent on the value of the link selection CSR: 
 * XPREUT_ENG_LTRCON.LinkSelect[1:0]. 
 */
typedef union {
  struct {
    UINT32 tstinitiated : 1;
    /* tstinitiated - Bits[0:0], RO_V, default = 1'b0 
       When the Tx-master sends RACK this bit will be set. Gets cleared with start test 
       bit getting reset, CSR: XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 errchkstart : 1;
    /* errchkstart - Bits[1:1], RO_V, default = 1'b0 
       Error check start
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 tstcomplete : 1;
    /* tstcomplete - Bits[2:2], RO_V, default = 1'b0 
       Test completed
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 masterrelck : 1;
    /* masterrelck - Bits[3:3], RO_V, default = 1'b0 
       Master relock acheived
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 anylaneerr : 1;
    /* anylaneerr - Bits[4:4], RO_V, default = 1'b0 
       Any lanes are have error
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 alllaneerr : 1;
    /* alllaneerr - Bits[5:5], RO_V, default = 1'b0 
       All lanes are have error
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 anylaneovflw : 1;
    /* anylaneovflw - Bits[6:6], RO_V, default = 1'b0 
       Any lanes are have error overflow
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 alllaneovflw : 1;
    /* alllaneovflw - Bits[7:7], RO_V, default = 1'b0 
       All lanes are have error overflow
       This bit field is dependent on the value selected in the link selection CSR: 
       XPREUT_ENG_LTRCON.LinkSelect 
     */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} REUTPATTES_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */














/* OBEINJCTL_IIO_DFX_REG supported on:                                        */
/*       IVT_EP (0x40033240)                                                  */
/*       IVT_EX (0x40033240)                                                  */
/*       HSX (0x40033240)                                                     */
/*       BDX (0x40033240)                                                     */
/* Register default value:              0x00000000                            */
#define OBEINJCTL_IIO_DFX_REG 0x12004240
#if defined(IVT_HOST) || defined(HSX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file IVX\0.6.3.CFG.xml.
 * This register contains the error injection mask register to determine which bits 
 * get corrupted for error detection testing. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 32;
  } Bits;
  UINT32 Data;
} OBEINJCTL_IIO_DFX_IVT_HSX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(IVT_HOST) || defined(HSX_HOST) */



#if defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * This register contains the error injection mask register to determine which bits 
 * get corrupted for error detection testing. 
 */
typedef union {
  struct {
    UINT32 aeilceninj : 1;
    /* aeilceninj - Bits[0:0], RWS_L, default = 1'b0 
       0: Disable error injection
       1: Enable error injection
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 aeilcinj1 : 1;
    /* aeilcinj1 - Bits[1:1], RWS_L, default = 1'b0 
       0: Select EINJ0 response function
       1: Select EINJ1 response function
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 rsvd_2 : 1;
    /* rsvd_2 - Bits[2:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 etrans_en : 1;
    /* etrans_en - Bits[3:3], RWS_L, default = 1'b0 
       0: do not inject this type of error
       1: inject an error based on the bit fields ETRANS and EBITPOS. This assumes that 
       EINJEN=1 and EINJFUNCTSEL is pointing to the EINJ of interest. 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 ebitpos : 10;
    /* ebitpos - Bits[13:4], RWS_L, default = 10'b0000000000 
       Bit field can contain more than one bit for multi-bit error injection.
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 etrans : 6;
    /* etrans - Bits[19:14], RWS_L, default = 6'b000000 
       This field indicates which symbol contains the corrupted bit. A maximum depth of 
       64 is where the corruption could occur. 
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 crcerrinj : 1;
    /* crcerrinj - Bits[20:20], RWS_L, default = 1'b0 
       CRC error injectionSelects which type of injection will be performed when 
       EINJ0,1 is asserted. 
       
       0: Data bit corruption. Based ETRANS and EBITPOS values.
       1: CRC bit corruption. Based on values in PEX[6:0]EINJMSK.
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 stpinj : 1;
    /* stpinj - Bits[21:21], RWS_L, default = 1'b0 
       0: Do not inject error on STP
       1: Inject error on STP when EINJEN is set.
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 endinj : 1;
    /* endinj - Bits[22:22], RWS_L, default = 1'b0 
       0: Do not inject error on END
       1: Inject error on END when EINJEN is set
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 sdpinj : 1;
    /* sdpinj - Bits[23:23], RWS_L, default = 1'b0 
       0: Do not inject error on SDP
       1: Inject error on SDP when EINJEN is set
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 othrinj : 1;
    /* othrinj - Bits[24:24], RWS_L, default = 1'b0 
       0: Do not inject error on type Others
       1: Inject error on type Others when EINJEN is set
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 err_lane : 4;
    /* err_lane - Bits[28:25], RWS_L, default = 4'b0000 
       Select one of the 16 lanes to inject error on
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 rsvd_29 : 1;
    /* rsvd_29 - Bits[29:29], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 ecrcerrinj : 1;
    /* ecrcerrinj - Bits[30:30], RWS_L, default = 1'b0 
       ECRC error injectionSelects which type of injection will be performed when 
       EINJ0,1 is asserted. 
       
       0: No ECRC error injection
       1: ECRC bit corruption. Based on values in PEX[6:0]EINJMSK.
       ECRC and CRC uses same mask values
       
       Notes:
       Locked by SPARELCK
     */
    UINT32 disretryerr : 1;
    /* disretryerr - Bits[31:31], RWS_L, default = 1'b0 
       
       Notes:
       Locked by SPARELCK
     */
  } Bits;
  UINT32 Data;
} OBEINJCTL_IIO_DFX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (BDX_HOST) */





/* SPARE_IIO_DFX_REG supported on:                                            */
/*       IVT_EP (0x40033248)                                                  */
/*       IVT_EX (0x40033248)                                                  */
/*       HSX (0x40033248)                                                     */
/*       BDX (0x40033248)                                                     */
/* Register default value:              0x003FF000                            */
#define SPARE_IIO_DFX_REG 0x12004248
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x248
 */
typedef union {
  struct {
    UINT32 force_data_perr_once : 1;
    /* force_data_perr_once - Bits[0:0], RWS_LV, default = 1'b0  */
    UINT32 pmnak_idlecycle : 5;
    /* pmnak_idlecycle - Bits[5:1], RWS_L, default = 5'b00000 
       Notes:
       Locked by SPARELCK
     */
    UINT32 enable_gc2wakeupl1 : 1;
    /* enable_gc2wakeupl1 - Bits[6:6], RWS_L, default = 1'b0 
       Notes:
       Locked by SPARELCK
     */
    UINT32 enable_gc2controll1 : 1;
    /* enable_gc2controll1 - Bits[7:7], RWS_L, default = 1'b0 
       Notes:
       Locked by SPARELCK
     */
    UINT32 cgtt_sparebits : 4;
    /* cgtt_sparebits - Bits[11:8], RWS_L, default = 4'b0000 
       1
     */
    UINT32 txn_port_spare1 : 10;
    /* txn_port_spare1 - Bits[21:12], RWS_L, default = 10'b1111111111  */
    UINT32 txn_port_spare0 : 10;
    /* txn_port_spare0 - Bits[31:22], RWS_L, default = 10'b0000000000  */
  } Bits;
  UINT32 Data;
} SPARE_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* XPPRIVC_IIO_DFX_REG supported on:                                          */
/*       IVT_EP (0x40033268)                                                  */
/*       IVT_EX (0x40033268)                                                  */
/*       HSX (0x40033268)                                                     */
/*       BDX (0x40033268)                                                     */
/* Register default value on IVT_EP:    0x00000100                            */
/* Register default value on IVT_EX:    0x00000100                            */
/* Register default value on HSX:       0x00000000                            */
/* Register default value on BDX:       0x00000000                            */
#define XPPRIVC_IIO_DFX_REG 0x12004268


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.3.CFG.xml.
 * This register contains bits for the design team for defeature bits in the PCIe 
 * transaction layer. The architectural visible defeatures are placed here as well. 
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 4;
    /* rsvd_0 - Bits[3:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 notused0 : 4;
    /* notused0 - Bits[7:4], RWS, default = 4'b0000  */
    UINT32 rsvd_8 : 1;
    /* rsvd_8 - Bits[8:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 notused1 : 7;
    /* notused1 - Bits[15:9], RWS, default = 7'b0000000  */
    UINT32 rsvd_16 : 16;
    /* rsvd_16 - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} XPPRIVC_IIO_DFX_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* XPPRIVC1_IIO_DFX_REG supported on:                                         */
/*       IVT_EP (0x4003326C)                                                  */
/*       IVT_EX (0x4003326C)                                                  */
/*       HSX (0x4003326C)                                                     */
/*       BDX (0x4003326C)                                                     */
/* Register default value:              0x00000355                            */
#define XPPRIVC1_IIO_DFX_REG 0x1200426C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x26c
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 4;
    UINT32 hpmsirevalen : 1;
    /* hpmsirevalen - Bits[4:4], RWS, default = 1'b1  */
    UINT32 hpmsiclapsen : 1;
    /* hpmsiclapsen - Bits[5:5], RWS, default = 1'b0 
       1
     */
    UINT32 rsvd_6 : 26;
  } Bits;
  UINT32 Data;
} XPPRIVC1_IIO_DFX_STRUCT;
#endif /* ASM_INC */






























/* PORT_CTL_IIO_DFX_REG supported on:                                         */
/*       IVT_EP (0x40033300)                                                  */
/*       IVT_EX (0x40033300)                                                  */
/*       HSX (0x40033300)                                                     */
/*       BDX (0x40033300)                                                     */
/* Register default value on IVT_EP:    0x81300200                            */
/* Register default value on IVT_EX:    0x81300200                            */
/* Register default value on HSX:       0x81300000                            */
/* Register default value on BDX:       0x81300000                            */
#define PORT_CTL_IIO_DFX_REG 0x12004300


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x300
 */
typedef union {
  struct {
    UINT32 tx_rxdetect_en : 1;
    /* tx_rxdetect_en - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 tx_rxdetect_en_override_enable : 1;
    /* tx_rxdetect_en_override_enable - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 rsvd_2 : 2;
    /* rsvd_2 - Bits[3:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 nearend_lpbk_en : 1;
    /* nearend_lpbk_en - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 rsvd_5 : 7;
    /* rsvd_5 - Bits[11:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rx_invert_phasedet_slope : 1;
    /* rx_invert_phasedet_slope - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 rsvd_13 : 3;
    /* rsvd_13 - Bits[15:13], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rx_sum_bias_sel : 1;
    /* rx_sum_bias_sel - Bits[16:16], RWS_L, default = 1'b0  */
    UINT32 rsvd_17 : 3;
    /* rsvd_17 - Bits[19:17], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rx_dfesum_mfc_10gen : 2;
    /* rx_dfesum_mfc_10gen - Bits[21:20], RWS_L, default = 2'b11  */
    UINT32 rsvd_22 : 2;
    /* rsvd_22 - Bits[23:22], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rx_dfelsb_sel : 2;
    /* rx_dfelsb_sel - Bits[25:24], RWS_L, default = 2'b01  */
    UINT32 rsvd_26 : 2;
    /* rsvd_26 - Bits[27:26], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rx_dfe_c1_ctl_notgen2 : 2;
    /* rx_dfe_c1_ctl_notgen2 - Bits[29:28], RWS_L, default = 2'b00  */
    UINT32 rx_dfe_c1_ctl_gen2 : 2;
    /* rx_dfe_c1_ctl_gen2 - Bits[31:30], RWS_L, default = 2'b10  */
  } Bits;
  UINT32 Data;
} PORT_CTL_IIO_DFX_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */
























/* PXPPRTGEN3EQPRIV_IIO_DFX_REG supported on:                                 */
/*       IVT_EP (0x4003339C)                                                  */
/*       IVT_EX (0x4003339C)                                                  */
/*       HSX (0x4003339C)                                                     */
/*       BDX (0x4003339C)                                                     */
/* Register default value:              0x0024001E                            */
#define PXPPRTGEN3EQPRIV_IIO_DFX_REG 0x1200439C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x39c
 */
typedef union {
  struct {
    UINT32 dmplenfovrd : 1;
    /* dmplenfovrd - Bits[0:0], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_july0_7spec : 1;
    /* en_july0_7spec - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 bypass_txeqcoeff_rule4b : 1;
    /* bypass_txeqcoeff_rule4b - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 dis_txdcbal : 1;
    /* dis_txdcbal - Bits[3:3], RWS_L, default = 1'b1 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_rxdcbal : 1;
    /* dis_rxdcbal - Bits[4:4], RWS_L, default = 1'b1 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_ts_rxdcbalcheck : 1;
    /* en_ts_rxdcbalcheck - Bits[5:5], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_6 : 2;
    /* rsvd_6 - Bits[7:6], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 dis_mask_p2l_lnkup4eq : 1;
    /* dis_mask_p2l_lnkup4eq - Bits[8:8], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_eqph23 : 1;
    /* dis_eqph23 - Bits[9:9], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 bypass_g3eq : 1;
    /* bypass_g3eq - Bits[10:10], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 use_g3eqprivatecsrvalues : 1;
    /* use_g3eqprivatecsrvalues - Bits[11:11], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 use_g3eqprivcsr4adaptsm : 1;
    /* use_g3eqprivcsr4adaptsm - Bits[12:12], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_gen3dis200mstimer4eqfail : 1;
    /* en_gen3dis200mstimer4eqfail - Bits[13:13], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_check_dsc_reqeq : 1;
    /* dis_check_dsc_reqeq - Bits[14:14], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_setg3spdfailcsr_inrcvrlck : 1;
    /* dis_setg3spdfailcsr_inrcvrlck - Bits[15:15], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_setg3spdfailcsr_inrcvrcfg : 1;
    /* dis_setg3spdfailcsr_inrcvrcfg - Bits[16:16], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dsc_redoeq_woquiesceg : 1;
    /* dsc_redoeq_woquiesceg - Bits[17:17], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dsc_redoeqcnt : 2;
    /* dsc_redoeqcnt - Bits[19:18], RWS_L, default = 2'b01 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 redoeqcnt_1sttime : 2;
    /* redoeqcnt_1sttime - Bits[21:20], RWS_L, default = 2'b10 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 byp_adaptsm_but_capcoeff : 1;
    /* byp_adaptsm_but_capcoeff - Bits[22:22], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_23 : 7;
    /* rsvd_23 - Bits[29:23], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 en_g3skpos2osblkstart : 1;
    /* en_g3skpos2osblkstart - Bits[30:30], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 disable_fe9_fe5_framingerrs : 1;
    /* disable_fe9_fe5_framingerrs - Bits[31:31], RWS_L, default = 1'b0 
       1
     */
  } Bits;
  UINT32 Data;
} PXPPRTGEN3EQPRIV_IIO_DFX_STRUCT;
#endif /* ASM_INC */








/* GEN3PRIVTXEQ_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x400333AC)                                                  */
/*       IVT_EX (0x400333AC)                                                  */
/*       HSX (0x400333AC)                                                     */
/*       BDX (0x400333AC)                                                     */
/* Register default value:              0x001EFBEF                            */
#define GEN3PRIVTXEQ_IIO_DFX_REG 0x120043AC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x3ac
 */
typedef union {
  struct {
    UINT32 bndl0_g3ptxeq_cursor : 6;
    /* bndl0_g3ptxeq_cursor - Bits[5:0], RW_L, default = 6'b101111 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 bndl1_g3ptxeq_cursor : 6;
    /* bndl1_g3ptxeq_cursor - Bits[11:6], RW_L, default = 6'b101111 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 bndl0_g3ptxeq_postcursor : 5;
    /* bndl0_g3ptxeq_postcursor - Bits[16:12], RW_L, default = 5'b01111 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 bndl1_g3ptxeq_postcursor : 5;
    /* bndl1_g3ptxeq_postcursor - Bits[21:17], RW_L, default = 5'b01111 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 bndl0_g3ptxeq_precursor : 5;
    /* bndl0_g3ptxeq_precursor - Bits[26:22], RW_L, default = 5'b00000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 bndl1_g3ptxeq_precursor : 5;
    /* bndl1_g3ptxeq_precursor - Bits[31:27], RW_L, default = 5'b00000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} GEN3PRIVTXEQ_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* GEN3PRIVRMTTXEQ_IIO_DFX_REG supported on:                                  */
/*       IVT_EP (0x400333B0)                                                  */
/*       IVT_EX (0x400333B0)                                                  */
/*       HSX (0x400333B0)                                                     */
/*       BDX (0x400333B0)                                                     */
/* Register default value:              0x001EFBEF                            */
#define GEN3PRIVRMTTXEQ_IIO_DFX_REG 0x120043B0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x3b0
 */
typedef union {
  struct {
    UINT32 bndl0_g3prmttxeq_cursor : 6;
    /* bndl0_g3prmttxeq_cursor - Bits[5:0], RW_L, default = 6'b101111 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 bndl1_g3prmttxeq_cursor : 6;
    /* bndl1_g3prmttxeq_cursor - Bits[11:6], RW_L, default = 6'b101111 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 bndl0_g3prmttxeq_postcursor : 5;
    /* bndl0_g3prmttxeq_postcursor - Bits[16:12], RW_L, default = 5'b01111 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 bndl1_g3prmttxeq_postcursor : 5;
    /* bndl1_g3prmttxeq_postcursor - Bits[21:17], RW_L, default = 5'b01111 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 bndl0_g3prmttxeq_precursor : 5;
    /* bndl0_g3prmttxeq_precursor - Bits[26:22], RW_L, default = 5'b00000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 bndl1_g3prmttxeq_precursor : 5;
    /* bndl1_g3prmttxeq_precursor - Bits[31:27], RW_L, default = 5'b00000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} GEN3PRIVRMTTXEQ_IIO_DFX_STRUCT;
#endif /* ASM_INC */








/* PARTNER_TXEQ_FSSTAR_IIO_DFX_REG supported on:                              */
/*       IVT_EP (0x400333C0)                                                  */
/*       IVT_EX (0x400333C0)                                                  */
/*       HSX (0x400333C0)                                                     */
/*       BDX (0x400333C0)                                                     */
/* Register default value:              0x00000000                            */
#define PARTNER_TXEQ_FSSTAR_IIO_DFX_REG 0x120043C0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x3c0
 */
typedef union {
  struct {
    UINT32 patnerx4_txeq_fsstart : 24;
    /* patnerx4_txeq_fsstart - Bits[23:0], RO_V, default = 24'b000000000000000000000000 
       1
     */
    UINT32 adaptsmx4_reject_cntr : 8;
    /* adaptsmx4_reject_cntr - Bits[31:24], RO_V, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} PARTNER_TXEQ_FSSTAR_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TXEQMISCSTATUS_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x400333C4)                                                  */
/*       IVT_EX (0x400333C4)                                                  */
/*       HSX (0x400333C4)                                                     */
/*       BDX (0x400333C4)                                                     */
/* Register default value:              0x00000000                            */
#define TXEQMISCSTATUS_IIO_DFX_REG 0x120043C4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x3c4
 */
typedef union {
  struct {
    UINT32 patnerx4_txeq_lfstart : 24;
    /* patnerx4_txeq_lfstart - Bits[23:0], RO_V, default = 24'b000000000000000000000000 
       1
     */
    UINT32 g3eq_ph0_success : 1;
    /* g3eq_ph0_success - Bits[24:24], RW_V, default = 1'b0  */
    UINT32 rsvd : 7;
    /* rsvd - Bits[31:25], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TXEQMISCSTATUS_IIO_DFX_STRUCT;
#endif /* ASM_INC */




/* TX_PH3_CURSOR_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x400333CC)                                                  */
/*       IVT_EX (0x400333CC)                                                  */
/*       HSX (0x400333CC)                                                     */
/*       BDX (0x400333CC)                                                     */
/* Register default value:              0x00000000                            */
#define TX_PH3_CURSOR_IIO_DFX_REG 0x120043CC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x3cc
 */
typedef union {
  struct {
    UINT32 b0add_pre_cursor : 3;
    /* b0add_pre_cursor - Bits[2:0], RW_L, default = 3'b000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 b1add_pre_cursor : 3;
    /* b1add_pre_cursor - Bits[5:3], RW_L, default = 3'b000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 b0sub_pre_cursor : 3;
    /* b0sub_pre_cursor - Bits[8:6], RW_L, default = 3'b000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 b1sub_pre_cursor : 3;
    /* b1sub_pre_cursor - Bits[11:9], RW_L, default = 3'b000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 b0add_post_cursor : 3;
    /* b0add_post_cursor - Bits[14:12], RW_L, default = 3'b000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 b1add_post_cursor : 3;
    /* b1add_post_cursor - Bits[17:15], RW_L, default = 3'b000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 b0sub_post_cursor : 3;
    /* b0sub_post_cursor - Bits[20:18], RW_L, default = 3'b000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 b1sub_post_cursor : 3;
    /* b1sub_post_cursor - Bits[23:21], RW_L, default = 3'b000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 bypass_endcard_coeff : 1;
    /* bypass_endcard_coeff - Bits[24:24], RW_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 7;
    /* rsvd - Bits[31:25], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_PH3_CURSOR_IIO_DFX_STRUCT;
#endif /* ASM_INC */


















/* TXEQREUTPRIV_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x400333F0)                                                  */
/*       IVT_EX (0x400333F0)                                                  */
/*       HSX (0x400333F0)                                                     */
/*       BDX (0x400333F0)                                                     */
/* Register default value:              0x3C002000                            */
#define TXEQREUTPRIV_IIO_DFX_REG 0x120043F0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x3f0
 */
typedef union {
  struct {
    UINT32 rsvd : 1;
    /* rsvd - Bits[0:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 use_oddlane_polcmpl_captxpreset : 1;
    /* use_oddlane_polcmpl_captxpreset - Bits[1:1], RWS_L, default = 1'b0 
       1
     */
    UINT32 dis_txeqmargin : 1;
    /* dis_txeqmargin - Bits[2:2], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_sym89_comp : 1;
    /* dis_sym89_comp - Bits[3:3], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_sym67_comp : 1;
    /* dis_sym67_comp - Bits[4:4], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_g3eqts1gen : 1;
    /* dis_g3eqts1gen - Bits[5:5], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_g12eqts2gen : 1;
    /* dis_g12eqts2gen - Bits[6:6], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_g12eqts1gen : 1;
    /* dis_g12eqts1gen - Bits[7:7], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_cmp_nzecinrcvrlck : 1;
    /* dis_cmp_nzecinrcvrlck - Bits[8:8], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_cmp_00ecinrcvrlck : 1;
    /* dis_cmp_00ecinrcvrlck - Bits[9:9], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_cappreset4uc_ineqts2 : 1;
    /* en_cappreset4uc_ineqts2 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 bypass_adaptmytx4selfloopback : 1;
    /* bypass_adaptmytx4selfloopback - Bits[11:11], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 wait4_2tsinlpbkentryslave : 1;
    /* wait4_2tsinlpbkentryslave - Bits[12:12], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_eqts1_in_polactive : 1;
    /* dis_eqts1_in_polactive - Bits[13:13], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_eqts1_in_lbm : 1;
    /* dis_eqts1_in_lbm - Bits[14:14], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_check_ts1_req_coeff : 1;
    /* dis_check_ts1_req_coeff - Bits[15:15], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_check_eqts14lb : 1;
    /* dis_check_eqts14lb - Bits[16:16], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_check_eqts14cmpl : 1;
    /* dis_check_eqts14cmpl - Bits[17:17], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_eqts1cap_inpolactcfglnkws_g12 : 1;
    /* en_eqts1cap_inpolactcfglnkws_g12 - Bits[18:18], RWS_L, default = 1'b0  */
    UINT32 use_highesteverspeed4eqts2 : 1;
    /* use_highesteverspeed4eqts2 - Bits[19:19], RWS_L, default = 1'b0  */
    UINT32 dis_skpparityerr_log : 1;
    /* dis_skpparityerr_log - Bits[20:20], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_synchbitserr_log : 1;
    /* dis_synchbitserr_log - Bits[21:21], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 inph3eval_request2rsteiescntr : 1;
    /* inph3eval_request2rsteiescntr - Bits[22:22], RWS_L, default = 1'b0  */
    UINT32 en_ph3_tiemout2nongen3 : 1;
    /* en_ph3_tiemout2nongen3 - Bits[23:23], RWS_L, default = 1'b0  */
    UINT32 en_clear_g3spdfail_on200mstimer : 1;
    /* en_clear_g3spdfail_on200mstimer - Bits[24:24], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 use_reutep_txeqlvls : 1;
    /* use_reutep_txeqlvls - Bits[25:25], RWS_L, default = 1'b0  */
    UINT32 dis_sos_ing3lpbkpattern : 1;
    /* dis_sos_ing3lpbkpattern - Bits[26:26], RWS_L, default = 1'b1  */
    UINT32 dis_sos_ing3lpbkmarker : 1;
    /* dis_sos_ing3lpbkmarker - Bits[27:27], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_sos_ing12lpbkactive : 1;
    /* dis_sos_ing12lpbkactive - Bits[28:28], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 reutsel_onelaneperx4inslaveloopback : 1;
    /* reutsel_onelaneperx4inslaveloopback - Bits[29:29], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_g3osvalid_rstscramsignals : 1;
    /* dis_g3osvalid_rstscramsignals - Bits[30:30], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_throtreut4g3skpinsert : 1;
    /* dis_throtreut4g3skpinsert - Bits[31:31], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} TXEQREUTPRIV_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* UNIPHYPMCTL_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x400333F4)                                                  */
/*       IVT_EX (0x400333F4)                                                  */
/*       HSX (0x400333F4)                                                     */
/*       BDX (0x400333F4)                                                     */
/* Register default value:              0x8A250910                            */
#define UNIPHYPMCTL_IIO_DFX_REG 0x120043F4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x3f4
 */
typedef union {
  struct {
    UINT32 stagmode : 2;
    /* stagmode - Bits[1:0], RWS_L, default = 2'b00 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lanestagint : 4;
    /* lanestagint - Bits[5:2], RWS_L, default = 4'b0100 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_txsqfsm_l1idletime : 1;
    /* dis_txsqfsm_l1idletime - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 rsvd_7 : 1;
    /* rsvd_7 - Bits[7:7], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 rxsqex_cntrval : 4;
    /* rxsqex_cntrval - Bits[11:8], RWS_L, default = 4'b1001 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rxl1mskbits : 2;
    /* rxl1mskbits - Bits[13:12], RWS_L, default = 2'b00 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 force_rxsqexit : 1;
    /* force_rxsqexit - Bits[14:14], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 force_rxdetected : 1;
    /* force_rxdetected - Bits[15:15], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_rxrst4inferredei : 1;
    /* dis_rxrst4inferredei - Bits[16:16], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rst_sqexitflop : 1;
    /* rst_sqexitflop - Bits[17:17], RWS_L, default = 1'b0  */
    UINT32 en_uniphyl1_forfusedoffports : 1;
    /* en_uniphyl1_forfusedoffports - Bits[18:18], RWS_L, default = 1'b1  */
    UINT32 rsvd_19 : 1;
    /* rsvd_19 - Bits[19:19], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 txlanestagint : 4;
    /* txlanestagint - Bits[23:20], RWS_L, default = 4'b0010 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_txl0sentrystagger : 1;
    /* dis_txl0sentrystagger - Bits[24:24], RWS_L, default = 1'b0 
       1
     */
    UINT32 csr_rxsqfsm_l1exitwaittime_in32ns : 2;
    /* csr_rxsqfsm_l1exitwaittime_in32ns - Bits[26:25], RWS_L, default = 2'b01 
       Wait time before determining an exit from L1 really is happening.
       
       00: 32nS
       01: 64nS
       10: 96nS
       11: 128nS
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rxsqfsm_generic_waittime_in16ns : 3;
    /* rxsqfsm_generic_waittime_in16ns - Bits[29:27], RWS_L, default = 3'b001 
       Minimum time between L1 and L0s to uniphy.
       
       000: 16nS
       001: 32nS
       010: 48nS
       011: 64nS
       100: 80nS
       101: 96nS
       110: 112nS
       111: 128nS
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_extend_rxclkoff4bitlocktime : 1;
    /* en_extend_rxclkoff4bitlocktime - Bits[30:30], RWS_L, default = 1'b0 
       1
     */
    UINT32 en_txsqfsm_rst_on_ltdetect : 1;
    /* en_txsqfsm_rst_on_ltdetect - Bits[31:31], RWS_L, default = 1'b1 
       1
     */
  } Bits;
  UINT32 Data;
} UNIPHYPMCTL_IIO_DFX_STRUCT;
#endif /* ASM_INC */




/* TXEQREUTPRIV1_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x400333FC)                                                  */
/*       IVT_EX (0x400333FC)                                                  */
/*       HSX (0x400333FC)                                                     */
/*       BDX (0x400333FC)                                                     */
/* Register default value:              0x00000000                            */
#define TXEQREUTPRIV1_IIO_DFX_REG 0x120043FC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x3fc
 */
typedef union {
  struct {
    UINT32 ph3_500nstimerincreasein_1us : 10;
    /* ph3_500nstimerincreasein_1us - Bits[9:0], RWS_L, default = 10'b0000000000 
       The Phase 3 timer for 500nS can be programmed up to 1mS in increments of 1uS. 
       The value in this field specifies how many 1uS intervals to add to the 500nS 
       timer. 
       
       0: 500nS
       1: 1.5uS
       2: 2.5uS
       :
       :
       1023: 1.0235mS
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 22;
    /* rsvd - Bits[31:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TXEQREUTPRIV1_IIO_DFX_STRUCT;
#endif /* ASM_INC */








/* PCIE_IOT_LANE_SEL_REG_IIO_DFX_REG supported on:                            */
/*       BDX (0x4003341C)                                                     */
/* Register default value:              0x00000000                            */
#define PCIE_IOT_LANE_SEL_REG_IIO_DFX_REG 0x1200441C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x41c
 */
typedef union {
  struct {
    UINT32 lane_0_sel : 4;
    /* lane_0_sel - Bits[3:0], RWS_L, default = 4'b0000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_1_sel : 4;
    /* lane_1_sel - Bits[7:4], RWS_L, default = 4'b0000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_2_sel : 4;
    /* lane_2_sel - Bits[11:8], RWS_L, default = 4'b0000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_3_sel : 4;
    /* lane_3_sel - Bits[15:12], RWS_L, default = 4'b0000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_4_sel : 4;
    /* lane_4_sel - Bits[19:16], RWS_L, default = 4'b0000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_5_sel : 4;
    /* lane_5_sel - Bits[23:20], RWS_L, default = 4'b0000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_6_sel : 4;
    /* lane_6_sel - Bits[27:24], RWS_L, default = 4'b0000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_7_sel : 4;
    /* lane_7_sel - Bits[31:28], RWS_L, default = 4'b0000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} PCIE_IOT_LANE_SEL_REG_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */




/* PCIE_IOT_TRIG2_SEL_REG_IIO_DFX_REG supported on:                           */
/*       BDX (0x40033424)                                                     */
/* Register default value:              0x00000000                            */
#define PCIE_IOT_TRIG2_SEL_REG_IIO_DFX_REG 0x12004424

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x424
 */
typedef union {
  struct {
    UINT32 trig4_rx_sel : 6;
    /* trig4_rx_sel - Bits[5:0], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig5_rx_sel : 6;
    /* trig5_rx_sel - Bits[11:6], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig6_rx_sel : 6;
    /* trig6_rx_sel - Bits[17:12], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig7_rx_sel : 6;
    /* trig7_rx_sel - Bits[23:18], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig0_tx_sel : 6;
    /* trig0_tx_sel - Bits[29:24], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PCIE_IOT_TRIG2_SEL_REG_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* LTSSMDBG0_IIO_DFX_REG supported on:                                        */
/*       IVT_EP (0x40033428)                                                  */
/*       IVT_EX (0x40033428)                                                  */
/*       HSX (0x40033428)                                                     */
/*       BDX (0x40033428)                                                     */
/* Register default value:              0x20003821                            */
#define LTSSMDBG0_IIO_DFX_REG 0x12004428
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x428
 */
typedef union {
  struct {
    UINT32 disablenonedge0 : 1;
    /* disablenonedge0 - Bits[0:0], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 senddblidles : 1;
    /* senddblidles - Bits[1:1], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 checkhalftsrcvd : 1;
    /* checkhalftsrcvd - Bits[2:2], RWS_L, default = 1'b0 
       0: Make forward progress through the LTSSM as stated by PCIE cspec.
       1: Make forward progress if we receive half the # of TS sequences required by 
       the PCIE spec. 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 skpforsos : 1;
    /* skpforsos - Bits[3:3], RWS_L, default = 1'b0 
       0: Only discard SKP in EB if it is preceded by COM or SKP.
       1: Discard all SKPs from EB.
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 recrcvlockrecidleto : 1;
    /* recrcvlockrecidleto - Bits[4:4], RWS_L, default = 1'b0 
       0: Enter detect when timeout in REC IDLE happens.
       1: Enter rec.lock when timeout in rec.idle happens.
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 tssosforinferei : 1;
    /* tssosforinferei - Bits[5:5], RWS_L, default = 1'b1 
       When 1, use absence of TS/SOS to infer EI in L0.
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 sqexitforinferei : 1;
    /* sqexitforinferei - Bits[6:6], RWS_L, default = 1'b0 
       0: Use absence of TS/SOS to infer EI in L0.
       1: Use absence of sq exit in L0 to infer EI.
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 send256idles : 1;
    /* send256idles - Bits[7:7], RWS_L, default = 1'b0 
       0: Send min 16 idles, as specified in the PCIE cspec
       1: Send min 256 cycles of idle in REC.idle and CFG.idle before proceeding
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 forcereverse : 1;
    /* forcereverse - Bits[8:8], RWS_L, default = 1'b0 
       When set to 1 lane reversal is disabled and we use the value used in reverse_set 
       to select the reversal mode 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 disablex2 : 1;
    /* disablex2 - Bits[9:9], RWS_L, default = 1'b0 
       0: Enable x2 mode
       1: x2 mode is disabled, degrade straight to x1
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsmstateonts : 1;
    /* rsmstateonts - Bits[10:10], RWS_L, default = 1'b0 
       0: No debug info in TS sequences
       1: The rcv sm state is advertised in the upper 4 control bits of the TS 
       sequences 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 ebfullthold : 4;
    /* ebfullthold - Bits[14:11], RWS_L, default = 4'b0111 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 clrbitslip : 1;
    /* clrbitslip - Bits[15:15], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbgselltctl : 1;
    /* dbgselltctl - Bits[16:16], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 disgen3cfg : 1;
    /* disgen3cfg - Bits[17:17], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 disablesqinl0 : 3;
    /* disablesqinl0 - Bits[20:18], RWS_L, default = 3'b000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_rxclkoff2ebkl : 1;
    /* dis_rxclkoff2ebkl - Bits[21:21], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_cmp_tsparity : 1;
    /* dis_cmp_tsparity - Bits[22:22], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_g3recidle2reclck_wo2msto : 1;
    /* en_g3recidle2reclck_wo2msto - Bits[23:23], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 set_idle2rlck_max : 1;
    /* set_idle2rlck_max - Bits[24:24], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_gen3_seedovrd4x4_0 : 1;
    /* dis_gen3_seedovrd4x4_0 - Bits[25:25], RWS_L, default = 1'b0  */
    UINT32 dis_gen3_seedovrd4x4_1 : 1;
    /* dis_gen3_seedovrd4x4_1 - Bits[26:26], RWS_L, default = 1'b0  */
    UINT32 dis_gen3_seedovrd4x4_2 : 1;
    /* dis_gen3_seedovrd4x4_2 - Bits[27:27], RWS_L, default = 1'b0  */
    UINT32 dis_gen3_seedovrd4x4_3 : 1;
    /* dis_gen3_seedovrd4x4_3 - Bits[28:28], RWS_L, default = 1'b0  */
    UINT32 dis_nonedgeln0_reverse_combs : 1;
    /* dis_nonedgeln0_reverse_combs - Bits[29:29], RWS_L, default = 1'b1  */
    UINT32 dis_restart_shorttimer4w4rx2complete : 1;
    /* dis_restart_shorttimer4w4rx2complete - Bits[30:30], RWS_L, default = 1'b0  */
    UINT32 rsvd : 1;
    /* rsvd - Bits[31:31], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LTSSMDBG0_IIO_DFX_STRUCT;
#endif /* ASM_INC */








/* FSLFVAL_REG_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x40033438)                                                  */
/*       IVT_EX (0x40033438)                                                  */
/*       HSX (0x40033438)                                                     */
/*       BDX (0x40033438)                                                     */
/* Register default value:              0x0002057F                            */
#define FSLFVAL_REG_IIO_DFX_REG 0x12004438
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x438
 */
typedef union {
  struct {
    UINT32 fseqvalreg : 6;
    /* fseqvalreg - Bits[5:0], RWS_L, default = 6'b111111 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lfeqvalreg : 6;
    /* lfeqvalreg - Bits[11:6], RWS_L, default = 6'b010101 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 fsthreshold : 6;
    /* fsthreshold - Bits[17:12], RWS_L, default = 6'b100000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 14;
    /* rsvd - Bits[31:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} FSLFVAL_REG_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PCIE_IOT_LANE_TYPE_REG_IIO_DFX_REG supported on:                           */
/*       BDX (0x40033440)                                                     */
/* Register default value:              0x00000000                            */
#define PCIE_IOT_LANE_TYPE_REG_IIO_DFX_REG 0x12004440

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x440
 */
typedef union {
  struct {
    UINT32 local_or_remote : 1;
    /* local_or_remote - Bits[0:0], RWS_L, default = 1'b0 
       This is set to 1 to allow remote trace to pass through instead of the trace from 
       the local phy layer instance 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_0_rx_or_tx : 1;
    /* lane_0_rx_or_tx - Bits[1:1], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_1_rx_or_tx : 1;
    /* lane_1_rx_or_tx - Bits[2:2], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_2_rx_or_tx : 1;
    /* lane_2_rx_or_tx - Bits[3:3], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_3_rx_or_tx : 1;
    /* lane_3_rx_or_tx - Bits[4:4], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_4_rx_or_tx : 1;
    /* lane_4_rx_or_tx - Bits[5:5], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_5_rx_or_tx : 1;
    /* lane_5_rx_or_tx - Bits[6:6], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_6_rx_or_tx : 1;
    /* lane_6_rx_or_tx - Bits[7:7], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 lane_7_rx_or_tx : 1;
    /* lane_7_rx_or_tx - Bits[8:8], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 23;
    /* rsvd - Bits[31:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PCIE_IOT_LANE_TYPE_REG_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PCIE_IOT_TRIG1_SEL_REG_IIO_DFX_REG supported on:                           */
/*       BDX (0x40033444)                                                     */
/* Register default value:              0x00000000                            */
#define PCIE_IOT_TRIG1_SEL_REG_IIO_DFX_REG 0x12004444

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x444
 */
typedef union {
  struct {
    UINT32 trig_rx_lane_sel : 4;
    /* trig_rx_lane_sel - Bits[3:0], RWS_L, default = 4'b0000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig_tx_lane_sel : 4;
    /* trig_tx_lane_sel - Bits[7:4], RWS_L, default = 4'b0000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig0_rx_sel : 6;
    /* trig0_rx_sel - Bits[13:8], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig1_rx_sel : 6;
    /* trig1_rx_sel - Bits[19:14], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig2_rx_sel : 6;
    /* trig2_rx_sel - Bits[25:20], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig3_rx_sel : 6;
    /* trig3_rx_sel - Bits[31:26], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} PCIE_IOT_TRIG1_SEL_REG_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */










/* XPCBPHDELS1_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x40033458)                                                  */
/*       IVT_EX (0x40033458)                                                  */
/*       HSX (0x40033458)                                                     */
/*       BDX (0x40033458)                                                     */
/* Register default value:              0x00000000                            */
#define XPCBPHDELS1_IIO_DFX_REG 0x12004458


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.3.CFG.xml.
 * This register selects which set of debug event are available from this cluster 
 * for both display on the debug ring and for use in performance monitoring. Which 
 * set of debug events is selected is controllable on a lane-by-lane basis, meaning 
 * that each 8-bit lane can have a different set of debug events selected from any 
 * other lane. 
 */
typedef union {
  struct {
    UINT32 dbglnsel5 : 6;
    /* dbglnsel5 - Bits[5:0], RWS_L, default = 6'b000000 
       Selects the source for byte lane 5 of the Cluster Debug Bus from each 
       DebugEv_set. 
       000000: Byte lane 5 of Debug signal set 0
       000001: Byte lane 5 of Debug signal set 1
       ---
       111111: Byte lane 5 of Debug signal set 63
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbglnsel6 : 6;
    /* dbglnsel6 - Bits[11:6], RWS_L, default = 6'b000000 
       Selects the source for byte lane 6 of the Cluster Debug Bus from each 
       DebugEv_set. 
       000000: Byte lane 6 of Debug signal set 0
       000001: Byte lane 6 of Debug signal set 1
       ---
       111111: Byte lane 6 of Debug signal set 63
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbglnsel7 : 6;
    /* dbglnsel7 - Bits[17:12], RWS_L, default = 6'b000000 
       Selects the source for byte lane 7 of the Cluster Debug Bus from each 
       DebugEv_set. 
       000000: Byte lane 7 of Debug signal set 0
       000001: Byte lane 7 of Debug signal set 1
       ---
       111111: Byte lane 7 of Debug signal set 63
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbglnsel8 : 6;
    /* dbglnsel8 - Bits[23:18], RWS_L, default = 6'b000000 
       Selects the source for byte lane 8 of the Cluster Debug Bus from each 
       DebugEv_set. 
       000000: Byte lane 8 of Debug signal set 0
       000001: Byte lane 8 of Debug signal set 1
       ---
       111111: Byte lane 8 of Debug signal set 63
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 7;
    /* rsvd - Bits[30:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 afe_tracebus_en : 1;
    /* afe_tracebus_en - Bits[31:31], RWS_L, default = 1'b0 
       If 0, masks out the afe_tracebus_data input to the debug muxes (concerns over 
       determinism). 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} XPCBPHDELS1_IIO_DFX_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




/* PCIE_LANE_MASK_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x2003345C)                                                  */
/*       IVT_EX (0x2003345C)                                                  */
/*       HSX (0x2003345C)                                                     */
/*       BDX (0x2003345C)                                                     */
/* Register default value:              0x0000                                */
#define PCIE_LANE_MASK_IIO_DFX_REG 0x1200245C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x45c
 */
typedef union {
  struct {
    UINT16 lane_mask : 16;
    /* lane_mask - Bits[15:0], RWS_L, default = 16'b0000000000000000 
       This register is used by bios to mask individual lanes within the port 0, during 
       link training. A 1 in a bit indicates the corresponding lane is masked during 
       link training i.e. the lane will not be included in the link width negotiation 
       process. Software flow is that software will set the appropriate bits in this 
       register and then set the link retrain bit in the DEVCTRL register, of the 
       appropriate root port. 
       
       Note that this register does not control port bifurcation but rather controls 
       which lanes are included in link retraining within a bifurcated port. For 
       example, if Port 2 is already bifurcated to be two x8, and software wants to run 
       the upper x8 port in x2 width, then it would set, say, bits 15:10 in this 
       register and then set the link retrain bit in Device#2 root port. The upper x8 
       port would then train to a x2 on the lower two lanes of the x8 i.e. lanes 9:8. 
       
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT16 Data;
} PCIE_LANE_MASK_IIO_DFX_STRUCT;
#endif /* ASM_INC */




/* CLSPHYCTL1_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x40033464)                                                  */
/*       IVT_EX (0x40033464)                                                  */
/*       HSX (0x40033464)                                                     */
/*       BDX (0x40033464)                                                     */
/* Register default value on IVT_EP:    0x0070ACE3                            */
/* Register default value on IVT_EX:    0x0070ACE3                            */
/* Register default value on HSX:       0x0070A3E3                            */
/* Register default value on BDX:       0x0070A3E3                            */
#define CLSPHYCTL1_IIO_DFX_REG 0x12004464


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x464
 */
typedef union {
  struct {
    UINT32 force_2time_calibration : 1;
    /* force_2time_calibration - Bits[0:0], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 force_3time_calibration : 1;
    /* force_3time_calibration - Bits[1:1], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 force_bypass_calibration : 1;
    /* force_bypass_calibration - Bits[2:2], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 calibration_time_in64us : 4;
    /* calibration_time_in64us - Bits[6:3], RWS_L, default = 4'b1100 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 speedchangetime_constin4us : 6;
    /* speedchangetime_constin4us - Bits[12:7], RWS_L, default = 6'b000111 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 speedchangetime_gen3in1us : 6;
    /* speedchangetime_gen3in1us - Bits[18:13], RWS_L, default = 6'b000101 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 icompcalib_time_in64us : 4;
    /* icompcalib_time_in64us - Bits[22:19], RWS_L, default = 4'b1110 
       1
     */
    UINT32 oneus_timer_value : 9;
    /* oneus_timer_value - Bits[31:23], RWS_L, default = 9'b000000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} CLSPHYCTL1_IIO_DFX_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */












/* CLSPHYCTL6_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x40033478)                                                  */
/*       IVT_EX (0x40033478)                                                  */
/*       HSX (0x40033478)                                                     */
/*       BDX (0x40033478)                                                     */
/* Register default value:              0x42F9FE00                            */
#define CLSPHYCTL6_IIO_DFX_REG 0x12004478
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x478
 */
typedef union {
  struct {
    UINT32 dskindexmsk : 18;
    /* dskindexmsk - Bits[17:0], RWS_L, default = 18'b011111111000000000  */
    UINT32 dis_reccfg2recidle_ontoing3 : 1;
    /* dis_reccfg2recidle_ontoing3 - Bits[18:18], RWS_L, default = 1'b0  */
    UINT32 dis_uniphyrxrst4l0inferei : 1;
    /* dis_uniphyrxrst4l0inferei - Bits[19:19], RWS_L, default = 1'b1  */
    UINT32 dis_uniphyrxrst4recspdinferei : 1;
    /* dis_uniphyrxrst4recspdinferei - Bits[20:20], RWS_L, default = 1'b1  */
    UINT32 dis_uniphyrxrst4detectrecombine : 1;
    /* dis_uniphyrxrst4detectrecombine - Bits[21:21], RWS_L, default = 1'b1  */
    UINT32 dis_recspeedexit2w4bitlock1state : 1;
    /* dis_recspeedexit2w4bitlock1state - Bits[22:22], RWS_L, default = 1'b1  */
    UINT32 dis_check4sqexit : 1;
    /* dis_check4sqexit - Bits[23:23], RWS_L, default = 1'b1  */
    UINT32 recspdbitlock1toms : 4;
    /* recspdbitlock1toms - Bits[27:24], RWS_L, default = 4'b0010  */
    UINT32 en_ph3eval_256loopsonly : 1;
    /* en_ph3eval_256loopsonly - Bits[28:28], RWS_L, default = 1'b0  */
    UINT32 ph3eval_256loopcount : 2;
    /* ph3eval_256loopcount - Bits[30:29], RWS_L, default = 2'b10  */
    UINT32 en_indeppull4reccomplete : 1;
    /* en_indeppull4reccomplete - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} CLSPHYCTL6_IIO_DFX_STRUCT;
#endif /* ASM_INC */




/* CLSPHYCTL8_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x40033480)                                                  */
/*       IVT_EX (0x40033480)                                                  */
/*       HSX (0x40033480)                                                     */
/*       BDX (0x40033480)                                                     */
/* Register default value:              0xA6000FE2                            */
#define CLSPHYCTL8_IIO_DFX_REG 0x12004480
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x480
 */
typedef union {
  struct {
    UINT32 disable_blkcheck_failed_once : 1;
    /* disable_blkcheck_failed_once - Bits[0:0], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 enable_eiestrackfsm : 1;
    /* enable_eiestrackfsm - Bits[1:1], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_g3dvalid_beforeblklck : 1;
    /* en_g3dvalid_beforeblklck - Bits[2:2], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_lbslave_w4kalignlck : 1;
    /* dis_lbslave_w4kalignlck - Bits[3:3], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dis_2skpsing3lpbk : 1;
    /* dis_2skpsing3lpbk - Bits[4:4], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 spare1 : 4;
    /* spare1 - Bits[8:5], RWS_L, default = 4'b1111  */
    UINT32 rxsqexitw4alllanes : 1;
    /* rxsqexitw4alllanes - Bits[9:9], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 en_ltidlestate2rxl0s : 1;
    /* en_ltidlestate2rxl0s - Bits[10:10], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 indep_pull_rec_l0s : 1;
    /* indep_pull_rec_l0s - Bits[11:11], RWS_L, default = 1'b1 
       0: Do not pull data from elastic buffers.
       1: Pull data from elastic buffers.
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 disable_kalign : 1;
    /* disable_kalign - Bits[12:12], RWS_L, default = 1'b0 
       0: K-align enable
       1: K-align disable
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbl_ts_send : 1;
    /* dbl_ts_send - Bits[13:13], RWS_L, default = 1'b0 
       0: Send the standard quantity of TS sets.
       1: Send 2x the number of TS sets. Except for polling.active.
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 spare0 : 5;
    /* spare0 - Bits[18:14], RWS_L, default = 5'b00000 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 split_in_polling : 1;
    /* split_in_polling - Bits[19:19], RWS_L, default = 1'b0 
       0: Split the LTSSM in detect, based on ports activating at a different times
       1: Split the LTSSM in polling based on when data is received on the different 
       lanes 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 idlefrxd : 1;
    /* idlefrxd - Bits[20:20], RWS_L, default = 1'b0 
       0: Do not use 'exitei'
       1: Use 'exitei' signal to override rcv_detect.
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 endynlnk : 1;
    /* endynlnk - Bits[21:21], RWS_L, default = 1'b0 
       Enables the dynamic auto-negotiating with re-splitting or re-combining of the 
       LTSSM. 
       
       0: Disable dynamic auto-neg
       1: Enable dynamic auto-neg
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 spldet : 1;
    /* spldet - Bits[22:22], RWS_L, default = 1'b0 
       0: Enable LTSSM splitting
       1: Disable LTSSM splitting
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 discomp : 1;
    /* discomp - Bits[23:23], RWS_L, default = 1'b0 
       0: Enable loopback skip compensation
       1: Disable loopback skip compensation
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 disrec2cfgalgn : 1;
    /* disrec2cfgalgn - Bits[24:24], RWS_L, default = 1'b0 
       0: Reset kalign on recovery to cfg transition.
       1: Don't reset kalign on recovery to cfg transition.
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 enrecalgn : 1;
    /* enrecalgn - Bits[25:25], RWS_L, default = 1'b1 
       0: Don't reset kalign in recovery.
       1: Reset kalign in recovery.
       
       Notes:
       Locked by DBGBUSLCK
       
     */
    UINT32 loadgensup : 1;
    /* loadgensup - Bits[26:26], RWS_L, default = 1'b1 
       TX Loadgen SuppressSetting this bit prevents the Tx of the lane that was already 
       up in an up-config situation from getting re-synced by suppressing the 
       opxploadgen signal, otherwise a re-sync will occur. 
       
       Notes:
       if this bit is set = 0, the re-sync of the Tx in the lane that was still up may 
       potentially cause a bit slip and loss of symbol lock in the far-end device for 
       that lane. 
       Affects AFE signal called: opxploadgenen
       Locked by DBGBUSLCK
     */
    UINT32 lnknumtightcheck : 1;
    /* lnknumtightcheck - Bits[27:27], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 delaybankchange : 1;
    /* delaybankchange - Bits[28:28], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 cldatainsq : 1;
    /* cldatainsq - Bits[29:29], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 drcchangel0s : 1;
    /* drcchangel0s - Bits[30:30], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 gate_on_all_queues : 1;
    /* gate_on_all_queues - Bits[31:31], RWS_L, default = 1'b1 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} CLSPHYCTL8_IIO_DFX_STRUCT;
#endif /* ASM_INC */




/* PRTPHYCTL_IIO_DFX_REG supported on:                                        */
/*       IVT_EP (0x4003348C)                                                  */
/*       IVT_EX (0x4003348C)                                                  */
/*       HSX (0x4003348C)                                                     */
/*       BDX (0x4003348C)                                                     */
/* Register default value:              0x00020000                            */
#define PRTPHYCTL_IIO_DFX_REG 0x1200448C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x48c
 */
typedef union {
  struct {
    UINT32 rsvd_0 : 16;
    /* rsvd_0 - Bits[15:0], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 forcelnkingen2 : 1;
    /* forcelnkingen2 - Bits[16:16], RWS_L, default = 1'b0 
       0: Do not force gen2
       1: Force gen2 mode
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 contdeskew : 1;
    /* contdeskew - Bits[17:17], RWS_L, default = 1'b1 
       0: Disable dynamic deskew
       1: Enable dynamic deskew
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 cfgdeskewskp_g1g2 : 1;
    /* cfgdeskewskp_g1g2 - Bits[18:18], RWS_L, default = 1'b0 
       0: Do not select deskew
       1: Select deskew on SOS or TS in cfg.idle
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rcvrydeskewskp_g1g2 : 1;
    /* rcvrydeskewskp_g1g2 - Bits[19:19], RWS_L, default = 1'b0 
       0: Do not select deskew
       1: Select deskew on SOS or TS in recovery
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 csr_dmi_port : 1;
    /* csr_dmi_port - Bits[20:20], RWS_L, default = 1'b0 
       0: Do not operate link in DMI mode (DEFAULT for non DMI)
       1: Link operates in DMI mode (this results in a shorter detect TO and no rcv 
       detect) 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 wait_rcvrcfg_till_skp_sent : 1;
    /* wait_rcvrcfg_till_skp_sent - Bits[21:21], RWS_L, default = 1'b0 
       0: Don't wait for SKP to be sent before sending Rcvr config
       1: Send Rcvr config after SKP is sent
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 directed_spd_chg : 1;
    /* directed_spd_chg - Bits[22:22], RWS_L, default = 1'b0 
       This bit is not used.
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 csr_disable_linkdown : 1;
    /* csr_disable_linkdown - Bits[23:23], RWS_L, default = 1'b0 
       0: Enable linkdown
       1: Disable linkdown
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 kalign_mode : 2;
    /* kalign_mode - Bits[25:24], RWS_L, default = 2'b00 
       00: Dynamic all the time
       01: Static K-align
       10: Dynamic up to L0.
       11: Static K-align
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 enable_gen3scram_inreut : 1;
    /* enable_gen3scram_inreut - Bits[26:26], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 cfgdeskewskp_g3 : 1;
    /* cfgdeskewskp_g3 - Bits[27:27], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rcvrydeskewskp_g3 : 1;
    /* rcvrydeskewskp_g3 - Bits[28:28], RWS_L, default = 1'b0 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd_29 : 2;
    /* rsvd_29 - Bits[30:29], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 forcelnkingen3 : 1;
    /* forcelnkingen3 - Bits[31:31], RWS_L, default = 1'b0 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} PRTPHYCTL_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PXPSQCNT_IIO_DFX_REG supported on:                                         */
/*       IVT_EP (0x20033490)                                                  */
/*       IVT_EX (0x20033490)                                                  */
/*       HSX (0x20033490)                                                     */
/*       BDX (0x20033490)                                                     */
/* Register default value:              0x0001                                */
#define PXPSQCNT_IIO_DFX_REG 0x12002490
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x490
 */
typedef union {
  struct {
    UINT16 sqcnt : 13;
    /* sqcnt - Bits[12:0], RWS_L, default = 13'b0000000000001 
       The core logic splits this register into two effective fields:
       The lower 5 bits [4:0] is the delay in milliseconds after reset before DETECT 
       should start in normal operation. (Default: 1h -> 1 ms) 
       The upper 8 bits [12:5] is the number of 4ns-cycles after reset before DETECT 
       should start in HVM mode. (Default: 0h -> 0 cycles) 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT16 rsvd : 3;
    /* rsvd - Bits[15:13], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} PXPSQCNT_IIO_DFX_STRUCT;
#endif /* ASM_INC */




















/* DEBUGCLUSTER1_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x400334BC)                                                  */
/*       IVT_EX (0x400334BC)                                                  */
/*       HSX (0x400334BC)                                                     */
/*       BDX (0x400334BC)                                                     */
/* Register default value:              0x00039075                            */
#define DEBUGCLUSTER1_IIO_DFX_REG 0x120044BC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x4bc
 */
typedef union {
  struct {
    UINT32 leakagewa : 1;
    /* leakagewa - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 always2rcvdet : 1;
    /* always2rcvdet - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 eninfei : 1;
    /* eninfei - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 enperiodicexitei : 1;
    /* enperiodicexitei - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 recexiteito : 8;
    /* recexiteito - Bits[11:4], RWS_L, default = 8'b00000111  */
    UINT32 enforcedrec : 1;
    /* enforcedrec - Bits[12:12], RWS_L, default = 1'b1  */
    UINT32 send10bdataonerr : 1;
    /* send10bdataonerr - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 dbleiescount : 1;
    /* dbleiescount - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 enableeies : 1;
    /* enableeies - Bits[15:15], RWS_L, default = 1'b1  */
    UINT32 disgen2nogen2ts : 1;
    /* disgen2nogen2ts - Bits[16:16], RWS_L, default = 1'b1  */
    UINT32 flushebonrxclkoff : 1;
    /* flushebonrxclkoff - Bits[17:17], RWS_L, default = 1'b1  */
    UINT32 forcereconmissedsos : 1;
    /* forcereconmissedsos - Bits[18:18], RWS_L, default = 1'b0  */
    UINT32 l1exiteito : 8;
    /* l1exiteito - Bits[26:19], RWS_L, default = 8'b00000000  */
    UINT32 spare_signals : 5;
    /* spare_signals - Bits[31:27], RWS_L, default = 5'b00000  */
  } Bits;
  UINT32 Data;
} DEBUGCLUSTER1_IIO_DFX_STRUCT;
#endif /* ASM_INC */




/* PXPRETRYCTRL3_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x400334C4)                                                  */
/*       IVT_EX (0x400334C4)                                                  */
/*       HSX (0x400334C4)                                                     */
/*       BDX (0x400334C4)                                                     */
/* Register default value:              0x00010003                            */
#define PXPRETRYCTRL3_IIO_DFX_REG 0x120044C4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x4c4
 */
typedef union {
  struct {
    UINT32 replay_timer : 6;
    /* replay_timer - Bits[5:0], RWS_L, default = 6'b000011 
       Specifies in us the time after which a replay will be initiated. Setting it to 0 
       will disable the timer. The timer has an accuracy of +-1us 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 unuseentrinrtrybuf : 8;
    /* unuseentrinrtrybuf - Bits[13:6], RWS_L, default = 8'b00000000 
       1
     */
    UINT32 reinit_threshold : 3;
    /* reinit_threshold - Bits[16:14], RWS_L, default = 3'b100 
       Specifies the number of retry attempts after which a recovery will be initiated.
       
       Notes:
       Locked by DBGBUSLCK
       Logic 0 is an illegal setting.
     */
    UINT32 rsvd : 15;
    /* rsvd - Bits[31:17], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPRETRYCTRL3_IIO_DFX_STRUCT;
#endif /* ASM_INC */










/* XPCBLKDELS13_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x400334D8)                                                  */
/*       IVT_EX (0x400334D8)                                                  */
/*       HSX (0x400334D8)                                                     */
/*       BDX (0x400334D8)                                                     */
/* Register default value:              0x00000000                            */
#define XPCBLKDELS13_IIO_DFX_REG 0x120044D8


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.3.CFG.xml.
 * This register selects which set of debug events are available from this cluster 
 * for both display on the debug ring and for use in performance monitoring. Which 
 * set of debug events is selected is controllable on a lane-by-lane basis, meaning 
 * that each 8-bit lane can have a different set of debug events selected from any 
 * other lane. 
 */
typedef union {
  struct {
    UINT32 dbgevsel5 : 6;
    /* dbgevsel5 - Bits[5:0], RWS_L, default = 6'b000000 
       Selects the source for byte lane 5 of the Cluster Debug Bus from each 
       DebugEv_set. 
       000000: Byte lane 5 of Debug signal set 0
       000001: Byte lane 5 of Debug signal set 1
       ---
       111111: Byte lane 5 of Debug signal set 63
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbgevsel6 : 6;
    /* dbgevsel6 - Bits[11:6], RWS_L, default = 6'b000000 
       Selects the source for byte lane 6 of the Cluster Debug Bus from each 
       DebugEv_set. 
       000000: Byte lane 6 of Debug signal set 0
       000001: Byte lane 6 of Debug signal set 1
       ---
       111111: Byte lane 6 of Debug signal set 63
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbgevsel7 : 6;
    /* dbgevsel7 - Bits[17:12], RWS_L, default = 6'b000000 
       Selects the source for byte lane 7 of the Cluster Debug Bus from each 
       DebugEv_set. 
       000000: Byte lane 7 of Debug signal set 0
       000001: Byte lane 7 of Debug signal set 1
       ---
       111111: Byte lane 7 of Debug signal set 63
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 dbgevsel8 : 6;
    /* dbgevsel8 - Bits[23:18], RWS_L, default = 6'b000000 
       Selects the source for byte lane 8 of the Cluster Debug Bus from each 
       DebugEv_set. 
       000000: Byte lane 8 of Debug signal set 0
       000001: Byte lane 8 of Debug signal set 1
       ---
       111111: Byte lane 8 of Debug signal set 63
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 8;
    /* rsvd - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} XPCBLKDELS13_IIO_DFX_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */






/* PXPPMCTRL_IIO_DFX_REG supported on:                                        */
/*       IVT_EP (0x200334E0)                                                  */
/*       IVT_EX (0x200334E0)                                                  */
/*       HSX (0x200334E0)                                                     */
/*       BDX (0x200334E0)                                                     */
/* Register default value:              0x2006                                */
#define PXPPMCTRL_IIO_DFX_REG 0x120024E0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x4e0
 */
typedef union {
  struct {
    UINT16 l1_idle_timer : 5;
    /* l1_idle_timer - Bits[4:0], RWS_L, default = 5'b00110 
       1
     */
    UINT16 rsvd_5 : 3;
    /* rsvd_5 - Bits[7:5], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT16 l0s_idle_timer : 4;
    /* l0s_idle_timer - Bits[11:8], RWS_L, default = 4'b0000 
       Indicates the amount of idle time in us after which an L0s transition will be 
       initiated. The timers have an accuracy of +-1us. A setting of 0 will disable L0s 
       transitions. This setting will increase the frequency at which the DLLP's are 
       issued to keep it under the spec limit of 7us of idle time. 
       
       Notes:
       Locked by DBGBUSLCK
     */
    UINT16 use_cr_l0s_idle_timer : 1;
    /* use_cr_l0s_idle_timer - Bits[12:12], RWS_O, default = 1'b0  */
    UINT16 en_gen3_high_bw : 1;
    /* en_gen3_high_bw - Bits[13:13], RWS_L, default = 1'b1 
       ivt specific bit enables the higher b.w. while in gen3
     */
    UINT16 rsvd_14 : 2;
    /* rsvd_14 - Bits[15:14], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT16 Data;
} PXPPMCTRL_IIO_DFX_STRUCT;
#endif /* ASM_INC */






/* EXPBERR0_IIO_DFX_REG supported on:                                         */
/*       HSX (0x400334EC)                                                     */
/*       BDX (0x400334EC)                                                     */
/* Register default value:              0x00000000                            */
#define EXPBERR0_IIO_DFX_REG 0x120044EC

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * There are no fields in this register.
 */
typedef union {
  struct {
    UINT32 unspecified : 1;
    /* unspecified - Bits[0:0], RW, default = 1'b0 
       No fields were specified for this register
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} EXPBERR0_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* EXPBERR1_IIO_DFX_REG supported on:                                         */
/*       HSX (0x400334F0)                                                     */
/*       BDX (0x400334F0)                                                     */
/* Register default value:              0x00000000                            */
#define EXPBERR1_IIO_DFX_REG 0x120044F0

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x4f0
 */
typedef union {
  struct {
    UINT32 unspecified : 1;
    /* unspecified - Bits[0:0], RW, default = 1'b0 
       No fields were specified for this register
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} EXPBERR1_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */














/* PCIE_IOT_TRIG3_SEL_REG_IIO_DFX_REG supported on:                           */
/*       BDX (0x4003352C)                                                     */
/* Register default value:              0x00000000                            */
#define PCIE_IOT_TRIG3_SEL_REG_IIO_DFX_REG 0x1200452C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x52c
 */
typedef union {
  struct {
    UINT32 trig1_tx_sel : 6;
    /* trig1_tx_sel - Bits[5:0], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig2_tx_sel : 6;
    /* trig2_tx_sel - Bits[11:6], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig3_tx_sel : 6;
    /* trig3_tx_sel - Bits[17:12], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig4_tx_sel : 6;
    /* trig4_tx_sel - Bits[23:18], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig5_tx_sel : 6;
    /* trig5_tx_sel - Bits[29:24], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PCIE_IOT_TRIG3_SEL_REG_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* PCIEBURST_ERR_CNTR_IIO_DFX_REG supported on:                               */
/*       BDX (0x40033530)                                                     */
/* Register default value:              0x00000000                            */
#define PCIEBURST_ERR_CNTR_IIO_DFX_REG 0x12004530

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x530
 */
typedef union {
  struct {
    UINT32 error_burst_mode : 2;
    /* error_burst_mode - Bits[1:0], RW, default = 2'b00 
       Error Burst Mode is used define the mode of Burst. For BDX below is the set of 
       Burst mode supported 
       00 -- Reserved
       01 -- Burst Mode 2
       10 -- Burst Mode 3
       11 -- Burst Mode 4
     */
    UINT32 error_burst_mode_en : 1;
    /* error_burst_mode_en - Bits[2:2], RW, default = 1'b0 
       Error Burst Mode Enable enables the Burst Mode 2/3/4.
     */
    UINT32 rsvd_3 : 5;
    /* rsvd_3 - Bits[7:3], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 burst_count : 8;
    /* burst_count - Bits[15:8], RW1CS, default = 8'b00000000 
       Error Burst Count value
     */
    UINT32 burst_overflow : 1;
    /* burst_overflow - Bits[16:16], RW1CS, default = 1'b0 
       Error Burst Overflow
     */
    UINT32 rsvd_17 : 15;
    /* rsvd_17 - Bits[31:17], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PCIEBURST_ERR_CNTR_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */








/* PXPDLLCREDITREG23_IIO_DFX_REG supported on:                                */
/*       IVT_EP (0x40033548)                                                  */
/*       IVT_EX (0x40033548)                                                  */
/*       HSX (0x40033548)                                                     */
/*       BDX (0x40033548)                                                     */
/* Register default value on IVT_EP:    0x008A7C3E                            */
/* Register default value on IVT_EX:    0x008A7C3E                            */
/* Register default value on HSX:       0x00B0A854                            */
/* Register default value on BDX:       0x00B0A854                            */
#define PXPDLLCREDITREG23_IIO_DFX_REG 0x12004548


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x548
 */
typedef union {
  struct {
    UINT32 swrf_num_nprh_x8 : 8;
    /* swrf_num_nprh_x8 - Bits[7:0], RWS_L, default = 8'b01010100  */
    UINT32 swrf_num_nprh_x16 : 8;
    /* swrf_num_nprh_x16 - Bits[15:8], RWS_L, default = 8'b10101000  */
    UINT32 swrf_num_prd_x4 : 12;
    /* swrf_num_prd_x4 - Bits[27:16], RWS_L, default = 12'b000010110000  */
    UINT32 rsvd : 4;
    /* rsvd - Bits[31:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PXPDLLCREDITREG23_IIO_DFX_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */




















/* LNKPSMICDTREG3_IIO_DFX_REG supported on:                                   */
/*       HSX (0x4003356C)                                                     */
/*       BDX (0x4003356C)                                                     */
/* Register default value:              0x00000000                            */
#define LNKPSMICDTREG3_IIO_DFX_REG 0x1200456C

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x56c
 */
typedef union {
  struct {
    UINT32 unspecified : 1;
    /* unspecified - Bits[0:0], RW, default = 1'b0 
       No fields were specified for this register
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LNKPSMICDTREG3_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* LNKPSMICDTREG4_IIO_DFX_REG supported on:                                   */
/*       HSX (0x40033570)                                                     */
/*       BDX (0x40033570)                                                     */
/* Register default value:              0x00000000                            */
#define LNKPSMICDTREG4_IIO_DFX_REG 0x12004570

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x570
 */
typedef union {
  struct {
    UINT32 unspecified : 1;
    /* unspecified - Bits[0:0], RW, default = 1'b0 
       No fields were specified for this register
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LNKPSMICDTREG4_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* LNKPSMICDTREG5_IIO_DFX_REG supported on:                                   */
/*       HSX (0x40033574)                                                     */
/*       BDX (0x40033574)                                                     */
/* Register default value:              0x00000000                            */
#define LNKPSMICDTREG5_IIO_DFX_REG 0x12004574

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x574
 */
typedef union {
  struct {
    UINT32 unspecified : 1;
    /* unspecified - Bits[0:0], RW, default = 1'b0 
       No fields were specified for this register
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LNKPSMICDTREG5_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* LNKPSMICDTREG6_IIO_DFX_REG supported on:                                   */
/*       HSX (0x40033578)                                                     */
/*       BDX (0x40033578)                                                     */
/* Register default value:              0x00000000                            */
#define LNKPSMICDTREG6_IIO_DFX_REG 0x12004578

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x578
 */
typedef union {
  struct {
    UINT32 unspecified : 1;
    /* unspecified - Bits[0:0], RW, default = 1'b0 
       No fields were specified for this register
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LNKPSMICDTREG6_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* LNKPSMICDTREG7_IIO_DFX_REG supported on:                                   */
/*       HSX (0x4003357C)                                                     */
/*       BDX (0x4003357C)                                                     */
/* Register default value:              0x00000000                            */
#define LNKPSMICDTREG7_IIO_DFX_REG 0x1200457C

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x57c
 */
typedef union {
  struct {
    UINT32 unspecified : 1;
    /* unspecified - Bits[0:0], RW, default = 1'b0 
       No fields were specified for this register
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LNKPSMICDTREG7_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* LNKPSMICDTREG8_IIO_DFX_REG supported on:                                   */
/*       HSX (0x40033580)                                                     */
/*       BDX (0x40033580)                                                     */
/* Register default value:              0x00000000                            */
#define LNKPSMICDTREG8_IIO_DFX_REG 0x12004580

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x580
 */
typedef union {
  struct {
    UINT32 unspecified : 1;
    /* unspecified - Bits[0:0], RW, default = 1'b0 
       No fields were specified for this register
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LNKPSMICDTREG8_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* LNKPSMICDTREG9_IIO_DFX_REG supported on:                                   */
/*       HSX (0x40033584)                                                     */
/*       BDX (0x40033584)                                                     */
/* Register default value:              0x00000000                            */
#define LNKPSMICDTREG9_IIO_DFX_REG 0x12004584

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x584
 */
typedef union {
  struct {
    UINT32 unspecified : 1;
    /* unspecified - Bits[0:0], RW, default = 1'b0 
       No fields were specified for this register
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LNKPSMICDTREG9_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* LNKPSMICDTREG10_IIO_DFX_REG supported on:                                  */
/*       HSX (0x40033588)                                                     */
/*       BDX (0x40033588)                                                     */
/* Register default value:              0x00000000                            */
#define LNKPSMICDTREG10_IIO_DFX_REG 0x12004588

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x588
 */
typedef union {
  struct {
    UINT32 unspecified : 1;
    /* unspecified - Bits[0:0], RW, default = 1'b0 
       No fields were specified for this register
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LNKPSMICDTREG10_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* LNKPSMICDTREG11_IIO_DFX_REG supported on:                                  */
/*       HSX (0x4003358C)                                                     */
/*       BDX (0x4003358C)                                                     */
/* Register default value:              0x00000000                            */
#define LNKPSMICDTREG11_IIO_DFX_REG 0x1200458C

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x58c
 */
typedef union {
  struct {
    UINT32 unspecified : 1;
    /* unspecified - Bits[0:0], RW, default = 1'b0 
       No fields were specified for this register
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LNKPSMICDTREG11_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */














/* LTSSMFPLAOUT0_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x400335B0)                                                  */
/*       IVT_EX (0x400335B0)                                                  */
/*       HSX (0x400335B0)                                                     */
/*       BDX (0x400335B0)                                                     */
/* Register default value:              0x00000000                            */
#define LTSSMFPLAOUT0_IIO_DFX_REG 0x120045B0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x5b0
 */
typedef union {
  struct {
    UINT32 ltssm8_outp0_val : 32;
    /* ltssm8_outp0_val - Bits[31:0], RWS_L, default = 32'b00000000000000000000000000000000 
       Notes:
       Locked by DBGBUSLCK
     */
  } Bits;
  UINT32 Data;
} LTSSMFPLAOUT0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* LTSSMFPLAOUT1_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x400335B4)                                                  */
/*       IVT_EX (0x400335B4)                                                  */
/*       HSX (0x400335B4)                                                     */
/*       BDX (0x400335B4)                                                     */
/* Register default value:              0x00000000                            */
#define LTSSMFPLAOUT1_IIO_DFX_REG 0x120045B4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x5b4
 */
typedef union {
  struct {
    UINT32 ltssm8_outp1_val : 4;
    /* ltssm8_outp1_val - Bits[3:0], RWS_L, default = 4'b0000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 ltssm8_outp_en : 20;
    /* ltssm8_outp_en - Bits[23:4], RWS_L, default = 20'b00000000000000000000 
       1
     */
    UINT32 rsvd : 8;
    /* rsvd - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LTSSMFPLAOUT1_IIO_DFX_STRUCT;
#endif /* ASM_INC */
























/* EXPBERR3_IIO_DFX_REG supported on:                                         */
/*       HSX (0x400335E4)                                                     */
/*       BDX (0x400335E4)                                                     */
/* Register default value:              0x00000000                            */
#define EXPBERR3_IIO_DFX_REG 0x120045E4

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x5e4
 */
typedef union {
  struct {
    UINT32 unspecified : 1;
    /* unspecified - Bits[0:0], RW, default = 1'b0 
       No fields were specified for this register
     */
    UINT32 rsvd : 31;
    /* rsvd - Bits[31:1], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} EXPBERR3_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */












/* LBC_PER_IOU_CONTROL_IIO_DFX_REG supported on:                              */
/*       IVT_EP (0x40033600)                                                  */
/*       IVT_EX (0x40033600)                                                  */
/*       HSX (0x40033600)                                                     */
/*       BDX (0x40033600)                                                     */
/* Register default value:              0x00000000                            */
#define LBC_PER_IOU_CONTROL_IIO_DFX_REG 0x12004600
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x600
 */
typedef union {
  struct {
    UINT32 lbc_start : 1;
    /* lbc_start - Bits[0:0], RW_LV, default = 1'b0  */
    UINT32 lbc_req : 2;
    /* lbc_req - Bits[2:1], RW_L, default = 2'b00  */
    UINT32 lbc_ld_sel : 6;
    /* lbc_ld_sel - Bits[8:3], RW_L, default = 6'b000000  */
    UINT32 rsvd_9 : 2;
    /* rsvd_9 - Bits[10:9], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 lbc_ln_sel0 : 2;
    /* lbc_ln_sel0 - Bits[12:11], RW_L, default = 2'b00  */
    UINT32 lbc_ln_sel1 : 2;
    /* lbc_ln_sel1 - Bits[14:13], RW_L, default = 2'b00  */
    UINT32 lbc_ln_sel2 : 2;
    /* lbc_ln_sel2 - Bits[16:15], RW_L, default = 2'b00  */
    UINT32 lbc_ln_sel3 : 2;
    /* lbc_ln_sel3 - Bits[18:17], RW_L, default = 2'b00  */
    UINT32 lbc_ln_sel4 : 2;
    /* lbc_ln_sel4 - Bits[20:19], RW_L, default = 2'b00  */
    UINT32 lbc_ln_sel5 : 2;
    /* lbc_ln_sel5 - Bits[22:21], RW_L, default = 2'b00  */
    UINT32 lbc_ln_sel6 : 2;
    /* lbc_ln_sel6 - Bits[24:23], RW_L, default = 2'b00  */
    UINT32 lbc_ln_sel7 : 2;
    /* lbc_ln_sel7 - Bits[26:25], RW_L, default = 2'b00  */
    UINT32 rsvd_27 : 3;
    /* rsvd_27 - Bits[29:27], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 cfg_cya_delay_rd_capture : 1;
    /* cfg_cya_delay_rd_capture - Bits[30:30], RW_L, default = 1'b0  */
    UINT32 rsvd_31 : 1;
    /* rsvd_31 - Bits[31:31], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LBC_PER_IOU_CONTROL_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* LBC_PER_IOU_DATA_IIO_DFX_REG supported on:                                 */
/*       IVT_EP (0x40033604)                                                  */
/*       IVT_EX (0x40033604)                                                  */
/*       HSX (0x40033604)                                                     */
/*       BDX (0x40033604)                                                     */
/* Register default value:              0x00000000                            */
#define LBC_PER_IOU_DATA_IIO_DFX_REG 0x12004604
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x604
 */
typedef union {
  struct {
    UINT32 lbc_data_valid : 1;
    /* lbc_data_valid - Bits[0:0], RW_LV, default = 1'b0  */
    UINT32 lbc_data : 14;
    /* lbc_data - Bits[14:1], RW_LV, default = 14'b00000000000000  */
    UINT32 rsvd : 17;
    /* rsvd - Bits[31:15], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} LBC_PER_IOU_DATA_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* NTL_RX_INVERT_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x40033610)                                                  */
/*       IVT_EX (0x40033610)                                                  */
/*       HSX (0x40033610)                                                     */
/*       BDX (0x40033610)                                                     */
/* Register default value:              0x00000000                            */
#define NTL_RX_INVERT_IIO_DFX_REG 0x12004610
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x610
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} NTL_RX_INVERT_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* NTL_TX_INVERT_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x40033614)                                                  */
/*       IVT_EX (0x40033614)                                                  */
/*       HSX (0x40033614)                                                     */
/*       BDX (0x40033614)                                                     */
/* Register default value:              0x00000000                            */
#define NTL_TX_INVERT_IIO_DFX_REG 0x12004614
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x614
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} NTL_TX_INVERT_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PCIE_IOT_TRIG4_SEL_REG_IIO_DFX_REG supported on:                           */
/*       BDX (0x40033618)                                                     */
/* Register default value:              0x00000000                            */
#define PCIE_IOT_TRIG4_SEL_REG_IIO_DFX_REG 0x12004618

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x618
 */
typedef union {
  struct {
    UINT32 trig6_tx_sel : 6;
    /* trig6_tx_sel - Bits[5:0], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig7_tx_sel : 6;
    /* trig7_tx_sel - Bits[11:6], RWS_L, default = 6'b000000 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig_rx_link_sel : 2;
    /* trig_rx_link_sel - Bits[13:12], RWS_L, default = 2'b00 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 trig_tx_link_sel : 2;
    /* trig_tx_link_sel - Bits[15:14], RWS_L, default = 2'b00 
       Notes:
       Locked by DBGBUSLCK
     */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PCIE_IOT_TRIG4_SEL_REG_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* TXALIGN_EN_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x40033648)                                                  */
/*       IVT_EX (0x40033648)                                                  */
/*       HSX (0x40033648)                                                     */
/*       BDX (0x40033648)                                                     */
/* Register default value:              0x0000FFFF                            */
#define TXALIGN_EN_IIO_DFX_REG 0x12004648
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x648
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b1  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b1  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b1  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b1  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b1  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b1  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b1  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b1  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b1  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b1  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b1  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TXALIGN_EN_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_RTERMDIS_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x40033660)                                                  */
/*       IVT_EX (0x40033660)                                                  */
/*       HSX (0x40033660)                                                     */
/*       BDX (0x40033660)                                                     */
/* Register default value:              0x00000000                            */
#define RX_RTERMDIS_IIO_DFX_REG 0x12004660
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x660
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 15;
    /* rsvd - Bits[30:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 override_enable : 1;
    /* override_enable - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} RX_RTERMDIS_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_RTERMPULLHIGHN_IIO_DFX_REG supported on:                                */
/*       IVT_EP (0x40033664)                                                  */
/*       IVT_EX (0x40033664)                                                  */
/*       HSX (0x40033664)                                                     */
/*       BDX (0x40033664)                                                     */
/* Register default value:              0x00000000                            */
#define RX_RTERMPULLHIGHN_IIO_DFX_REG 0x12004664
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x664
 */
typedef union {
  struct {
    UINT32 lane0 : 2;
    /* lane0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 lane1 : 2;
    /* lane1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 lane2 : 2;
    /* lane2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 lane3 : 2;
    /* lane3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 lane4 : 2;
    /* lane4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 lane5 : 2;
    /* lane5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 lane6 : 2;
    /* lane6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 lane7 : 2;
    /* lane7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 lane8 : 2;
    /* lane8 - Bits[17:16], RWS_L, default = 2'b00  */
    UINT32 lane9 : 2;
    /* lane9 - Bits[19:18], RWS_L, default = 2'b00  */
    UINT32 lane10 : 2;
    /* lane10 - Bits[21:20], RWS_L, default = 2'b00  */
    UINT32 lane11 : 2;
    /* lane11 - Bits[23:22], RWS_L, default = 2'b00  */
    UINT32 lane12 : 2;
    /* lane12 - Bits[25:24], RWS_L, default = 2'b00  */
    UINT32 lane13 : 2;
    /* lane13 - Bits[27:26], RWS_L, default = 2'b00  */
    UINT32 lane14 : 2;
    /* lane14 - Bits[29:28], RWS_L, default = 2'b00  */
    UINT32 lane15 : 2;
    /* lane15 - Bits[31:30], RWS_L, default = 2'b00  */
  } Bits;
  UINT32 Data;
} RX_RTERMPULLHIGHN_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_RTERMPULLHIGHP_IIO_DFX_REG supported on:                                */
/*       IVT_EP (0x4003366C)                                                  */
/*       IVT_EX (0x4003366C)                                                  */
/*       HSX (0x4003366C)                                                     */
/*       BDX (0x4003366C)                                                     */
/* Register default value:              0x00000000                            */
#define RX_RTERMPULLHIGHP_IIO_DFX_REG 0x1200466C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x66c
 */
typedef union {
  struct {
    UINT32 lane0 : 2;
    /* lane0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 lane1 : 2;
    /* lane1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 lane2 : 2;
    /* lane2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 lane3 : 2;
    /* lane3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 lane4 : 2;
    /* lane4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 lane5 : 2;
    /* lane5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 lane6 : 2;
    /* lane6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 lane7 : 2;
    /* lane7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 lane8 : 2;
    /* lane8 - Bits[17:16], RWS_L, default = 2'b00  */
    UINT32 lane9 : 2;
    /* lane9 - Bits[19:18], RWS_L, default = 2'b00  */
    UINT32 lane10 : 2;
    /* lane10 - Bits[21:20], RWS_L, default = 2'b00  */
    UINT32 lane11 : 2;
    /* lane11 - Bits[23:22], RWS_L, default = 2'b00  */
    UINT32 lane12 : 2;
    /* lane12 - Bits[25:24], RWS_L, default = 2'b00  */
    UINT32 lane13 : 2;
    /* lane13 - Bits[27:26], RWS_L, default = 2'b00  */
    UINT32 lane14 : 2;
    /* lane14 - Bits[29:28], RWS_L, default = 2'b00  */
    UINT32 lane15 : 2;
    /* lane15 - Bits[31:30], RWS_L, default = 2'b00  */
  } Bits;
  UINT32 Data;
} RX_RTERMPULLHIGHP_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RXSQ_EN_IIO_DFX_REG supported on:                                          */
/*       IVT_EP (0x40033674)                                                  */
/*       IVT_EX (0x40033674)                                                  */
/*       HSX (0x40033674)                                                     */
/*       BDX (0x40033674)                                                     */
/* Register default value:              0x0000FFFF                            */
#define RXSQ_EN_IIO_DFX_REG 0x12004674
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x674
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b1  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b1  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b1  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b1  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b1  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b1  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b1  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b1  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b1  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b1  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b1  */
    UINT32 rsvd : 15;
    /* rsvd - Bits[30:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 override_enable : 1;
    /* override_enable - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} RXSQ_EN_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RXSQ_CTRL_0_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x40033678)                                                  */
/*       IVT_EX (0x40033678)                                                  */
/*       HSX (0x40033678)                                                     */
/*       BDX (0x40033678)                                                     */
/* Register default value:              0x24924924                            */
#define RXSQ_CTRL_0_IIO_DFX_REG 0x12004678
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x678
 */
typedef union {
  struct {
    UINT32 lane0 : 3;
    /* lane0 - Bits[2:0], RWS_L, default = 3'b100  */
    UINT32 lane1 : 3;
    /* lane1 - Bits[5:3], RWS_L, default = 3'b100  */
    UINT32 lane2 : 3;
    /* lane2 - Bits[8:6], RWS_L, default = 3'b100  */
    UINT32 lane3 : 3;
    /* lane3 - Bits[11:9], RWS_L, default = 3'b100  */
    UINT32 lane4 : 3;
    /* lane4 - Bits[14:12], RWS_L, default = 3'b100  */
    UINT32 lane5 : 3;
    /* lane5 - Bits[17:15], RWS_L, default = 3'b100  */
    UINT32 lane6 : 3;
    /* lane6 - Bits[20:18], RWS_L, default = 3'b100  */
    UINT32 lane7 : 3;
    /* lane7 - Bits[23:21], RWS_L, default = 3'b100  */
    UINT32 lane8 : 3;
    /* lane8 - Bits[26:24], RWS_L, default = 3'b100  */
    UINT32 lane9 : 3;
    /* lane9 - Bits[29:27], RWS_L, default = 3'b100  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RXSQ_CTRL_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RXSQ_CTRL_1_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x4003367C)                                                  */
/*       IVT_EX (0x4003367C)                                                  */
/*       HSX (0x4003367C)                                                     */
/*       BDX (0x4003367C)                                                     */
/* Register default value:              0x00024924                            */
#define RXSQ_CTRL_1_IIO_DFX_REG 0x1200467C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x67c
 */
typedef union {
  struct {
    UINT32 lane10 : 3;
    /* lane10 - Bits[2:0], RWS_L, default = 3'b100  */
    UINT32 lane11 : 3;
    /* lane11 - Bits[5:3], RWS_L, default = 3'b100  */
    UINT32 lane12 : 3;
    /* lane12 - Bits[8:6], RWS_L, default = 3'b100  */
    UINT32 lane13 : 3;
    /* lane13 - Bits[11:9], RWS_L, default = 3'b100  */
    UINT32 lane14 : 3;
    /* lane14 - Bits[14:12], RWS_L, default = 3'b100  */
    UINT32 lane15 : 3;
    /* lane15 - Bits[17:15], RWS_L, default = 3'b100  */
    UINT32 rsvd : 14;
    /* rsvd - Bits[31:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RXSQ_CTRL_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RXSQ_DET_IIO_DFX_REG supported on:                                         */
/*       IVT_EP (0x40033680)                                                  */
/*       IVT_EX (0x40033680)                                                  */
/*       HSX (0x40033680)                                                     */
/*       BDX (0x40033680)                                                     */
/* Register default value:              0x00000000                            */
#define RXSQ_DET_IIO_DFX_REG 0x12004680
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x680
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RO_V, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RO_V, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RO_V, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RO_V, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RO_V, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RO_V, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RO_V, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RO_V, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RO_V, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RO_V, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RO_V, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RO_V, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RO_V, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RO_V, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RO_V, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RO_V, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RXSQ_DET_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_CTLE_OFFSET_EN_IIO_DFX_REG supported on:                                */
/*       IVT_EP (0x40033684)                                                  */
/*       IVT_EX (0x40033684)                                                  */
/*       HSX (0x40033684)                                                     */
/*       BDX (0x40033684)                                                     */
/* Register default value:              0x0000FFFF                            */
#define RX_CTLE_OFFSET_EN_IIO_DFX_REG 0x12004684
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x684
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b1  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b1  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b1  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b1  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b1  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b1  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b1  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b1  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b1  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b1  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b1  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_CTLE_OFFSET_EN_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* OVRD_PD_CK_4UI_2AGENT_IIO_DFX_REG supported on:                            */
/*       HSX (0x40033698)                                                     */
/*       BDX (0x40033698)                                                     */
/* Register default value:              0x00000000                            */
#define OVRD_PD_CK_4UI_2AGENT_IIO_DFX_REG 0x12004698

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x698
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} OVRD_PD_CK_4UI_2AGENT_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* RX_CTLE_VCM_OVRD_DIS_IIO_DFX_REG supported on:                             */
/*       IVT_EP (0x4003369C)                                                  */
/*       IVT_EX (0x4003369C)                                                  */
/*       HSX (0x4003369C)                                                     */
/*       BDX (0x4003369C)                                                     */
/* Register default value:              0x00000000                            */
#define RX_CTLE_VCM_OVRD_DIS_IIO_DFX_REG 0x1200469C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x69c
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_CTLE_VCM_OVRD_DIS_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_DFE_SUMMER_CTL_IIO_DFX_REG supported on:                                */
/*       IVT_EP (0x400336A0)                                                  */
/*       IVT_EX (0x400336A0)                                                  */
/*       HSX (0x400336A0)                                                     */
/*       BDX (0x400336A0)                                                     */
/* Register default value:              0xFFFFFFFF                            */
#define RX_DFE_SUMMER_CTL_IIO_DFX_REG 0x120046A0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6a0
 */
typedef union {
  struct {
    UINT32 lane0 : 2;
    /* lane0 - Bits[1:0], RWS_L, default = 2'b11  */
    UINT32 lane1 : 2;
    /* lane1 - Bits[3:2], RWS_L, default = 2'b11  */
    UINT32 lane2 : 2;
    /* lane2 - Bits[5:4], RWS_L, default = 2'b11  */
    UINT32 lane3 : 2;
    /* lane3 - Bits[7:6], RWS_L, default = 2'b11  */
    UINT32 lane4 : 2;
    /* lane4 - Bits[9:8], RWS_L, default = 2'b11  */
    UINT32 lane5 : 2;
    /* lane5 - Bits[11:10], RWS_L, default = 2'b11  */
    UINT32 lane6 : 2;
    /* lane6 - Bits[13:12], RWS_L, default = 2'b11  */
    UINT32 lane7 : 2;
    /* lane7 - Bits[15:14], RWS_L, default = 2'b11  */
    UINT32 lane8 : 2;
    /* lane8 - Bits[17:16], RWS_L, default = 2'b11  */
    UINT32 lane9 : 2;
    /* lane9 - Bits[19:18], RWS_L, default = 2'b11  */
    UINT32 lane10 : 2;
    /* lane10 - Bits[21:20], RWS_L, default = 2'b11  */
    UINT32 lane11 : 2;
    /* lane11 - Bits[23:22], RWS_L, default = 2'b11  */
    UINT32 lane12 : 2;
    /* lane12 - Bits[25:24], RWS_L, default = 2'b11  */
    UINT32 lane13 : 2;
    /* lane13 - Bits[27:26], RWS_L, default = 2'b11  */
    UINT32 lane14 : 2;
    /* lane14 - Bits[29:28], RWS_L, default = 2'b11  */
    UINT32 lane15 : 2;
    /* lane15 - Bits[31:30], RWS_L, default = 2'b11  */
  } Bits;
  UINT32 Data;
} RX_DFE_SUMMER_CTL_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_AFE_OFFSETCOR_OPENLOOP_IIO_DFX_REG supported on:                        */
/*       IVT_EP (0x400336A8)                                                  */
/*       IVT_EX (0x400336A8)                                                  */
/*       HSX (0x400336A8)                                                     */
/*       BDX (0x400336A8)                                                     */
/* Register default value:              0x00000000                            */
#define RX_AFE_OFFSETCOR_OPENLOOP_IIO_DFX_REG 0x120046A8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6a8
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_AFE_OFFSETCOR_OPENLOOP_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_AFE_OFFSETCOR_GAIN_IIO_DFX_REG supported on:                            */
/*       IVT_EP (0x400336AC)                                                  */
/*       IVT_EX (0x400336AC)                                                  */
/*       HSX (0x400336AC)                                                     */
/*       BDX (0x400336AC)                                                     */
/* Register default value:              0x00005555                            */
#define RX_AFE_OFFSETCOR_GAIN_IIO_DFX_REG 0x120046AC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6ac
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b01  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b01  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b01  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b01  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b01  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b01  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b01  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b01  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_AFE_OFFSETCOR_GAIN_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_SPARE_0_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x400336B0)                                                  */
/*       IVT_EX (0x400336B0)                                                  */
/*       HSX (0x400336B0)                                                     */
/*       BDX (0x400336B0)                                                     */
/* Register default value:              0x00000000                            */
#define RX_SPARE_0_IIO_DFX_REG 0x120046B0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6b0
 */
typedef union {
  struct {
    UINT32 lane0 : 4;
    /* lane0 - Bits[3:0], RWS_L, default = 4'b0000  */
    UINT32 lane1 : 4;
    /* lane1 - Bits[7:4], RWS_L, default = 4'b0000  */
    UINT32 lane2 : 4;
    /* lane2 - Bits[11:8], RWS_L, default = 4'b0000  */
    UINT32 lane3 : 4;
    /* lane3 - Bits[15:12], RWS_L, default = 4'b0000  */
    UINT32 lane4 : 4;
    /* lane4 - Bits[19:16], RWS_L, default = 4'b0000  */
    UINT32 lane5 : 4;
    /* lane5 - Bits[23:20], RWS_L, default = 4'b0000  */
    UINT32 lane6 : 4;
    /* lane6 - Bits[27:24], RWS_L, default = 4'b0000  */
    UINT32 lane7 : 4;
    /* lane7 - Bits[31:28], RWS_L, default = 4'b0000  */
  } Bits;
  UINT32 Data;
} RX_SPARE_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_SPARE_1_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x400336B4)                                                  */
/*       IVT_EX (0x400336B4)                                                  */
/*       HSX (0x400336B4)                                                     */
/*       BDX (0x400336B4)                                                     */
/* Register default value:              0x00000000                            */
#define RX_SPARE_1_IIO_DFX_REG 0x120046B4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6b4
 */
typedef union {
  struct {
    UINT32 lane8 : 4;
    /* lane8 - Bits[3:0], RWS_L, default = 4'b0000  */
    UINT32 lane9 : 4;
    /* lane9 - Bits[7:4], RWS_L, default = 4'b0000  */
    UINT32 lane10 : 4;
    /* lane10 - Bits[11:8], RWS_L, default = 4'b0000  */
    UINT32 lane11 : 4;
    /* lane11 - Bits[15:12], RWS_L, default = 4'b0000  */
    UINT32 lane12 : 4;
    /* lane12 - Bits[19:16], RWS_L, default = 4'b0000  */
    UINT32 lane13 : 4;
    /* lane13 - Bits[23:20], RWS_L, default = 4'b0000  */
    UINT32 lane14 : 4;
    /* lane14 - Bits[27:24], RWS_L, default = 4'b0000  */
    UINT32 lane15 : 4;
    /* lane15 - Bits[31:28], RWS_L, default = 4'b0000  */
  } Bits;
  UINT32 Data;
} RX_SPARE_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_LPCLK_SEL_CK0_IIO_DFX_REG supported on:                                 */
/*       IVT_EP (0x400336C0)                                                  */
/*       IVT_EX (0x400336C0)                                                  */
/*       HSX (0x400336C0)                                                     */
/*       BDX (0x400336C0)                                                     */
/* Register default value:              0x00000000                            */
#define RX_LPCLK_SEL_CK0_IIO_DFX_REG 0x120046C0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6c0
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_LPCLK_SEL_CK0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* FAREND_LPBK_EN_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x400336C4)                                                  */
/*       IVT_EX (0x400336C4)                                                  */
/*       HSX (0x400336C4)                                                     */
/*       BDX (0x400336C4)                                                     */
/* Register default value:              0x00000000                            */
#define FAREND_LPBK_EN_IIO_DFX_REG 0x120046C4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6c4
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} FAREND_LPBK_EN_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_VCM_DS_SEL_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x400336C8)                                                  */
/*       IVT_EX (0x400336C8)                                                  */
/*       HSX (0x400336C8)                                                     */
/*       BDX (0x400336C8)                                                     */
/* Register default value:              0x00000000                            */
#define RX_VCM_DS_SEL_IIO_DFX_REG 0x120046C8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6c8
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_VCM_DS_SEL_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_VCM_SUM_SEL_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x400336CC)                                                  */
/*       IVT_EX (0x400336CC)                                                  */
/*       HSX (0x400336CC)                                                     */
/*       BDX (0x400336CC)                                                     */
/* Register default value:              0x000000FF                            */
#define RX_VCM_SUM_SEL_IIO_DFX_REG 0x120046CC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6cc
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b1  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b1  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b1  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_VCM_SUM_SEL_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_VREF_SEL_GEN1_0_IIO_DFX_REG supported on:                               */
/*       IVT_EP (0x400336E0)                                                  */
/*       IVT_EX (0x400336E0)                                                  */
/*       HSX (0x400336E0)                                                     */
/*       BDX (0x400336E0)                                                     */
/* Register default value on IVT_EP:    0x1EF7BDEF                            */
/* Register default value on IVT_EX:    0x1EF7BDEF                            */
/* Register default value on HSX:       0x16B5AD6B                            */
/* Register default value on BDX:       0x16B5AD6B                            */
#define RX_VREF_SEL_GEN1_0_IIO_DFX_REG 0x120046E0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6e0
 */
typedef union {
  struct {
    UINT32 lane0 : 5;
    /* lane0 - Bits[4:0], RWS_L, default = 5'b01011  */
    UINT32 lane1 : 5;
    /* lane1 - Bits[9:5], RWS_L, default = 5'b01011  */
    UINT32 lane2 : 5;
    /* lane2 - Bits[14:10], RWS_L, default = 5'b01011  */
    UINT32 lane3 : 5;
    /* lane3 - Bits[19:15], RWS_L, default = 5'b01011  */
    UINT32 lane4 : 5;
    /* lane4 - Bits[24:20], RWS_L, default = 5'b01011  */
    UINT32 lane5 : 5;
    /* lane5 - Bits[29:25], RWS_L, default = 5'b01011  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_VREF_SEL_GEN1_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_VREF_SEL_GEN1_1_IIO_DFX_REG supported on:                               */
/*       IVT_EP (0x400336E4)                                                  */
/*       IVT_EX (0x400336E4)                                                  */
/*       HSX (0x400336E4)                                                     */
/*       BDX (0x400336E4)                                                     */
/* Register default value on IVT_EP:    0x1EF7BDEF                            */
/* Register default value on IVT_EX:    0x1EF7BDEF                            */
/* Register default value on HSX:       0x16B5AD6B                            */
/* Register default value on BDX:       0x16B5AD6B                            */
#define RX_VREF_SEL_GEN1_1_IIO_DFX_REG 0x120046E4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6e4
 */
typedef union {
  struct {
    UINT32 lane6 : 5;
    /* lane6 - Bits[4:0], RWS_L, default = 5'b01011  */
    UINT32 lane7 : 5;
    /* lane7 - Bits[9:5], RWS_L, default = 5'b01011  */
    UINT32 lane8 : 5;
    /* lane8 - Bits[14:10], RWS_L, default = 5'b01011  */
    UINT32 lane9 : 5;
    /* lane9 - Bits[19:15], RWS_L, default = 5'b01011  */
    UINT32 lane10 : 5;
    /* lane10 - Bits[24:20], RWS_L, default = 5'b01011  */
    UINT32 lane11 : 5;
    /* lane11 - Bits[29:25], RWS_L, default = 5'b01011  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_VREF_SEL_GEN1_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_VREF_SEL_GEN1_2_IIO_DFX_REG supported on:                               */
/*       IVT_EP (0x400336E8)                                                  */
/*       IVT_EX (0x400336E8)                                                  */
/*       HSX (0x400336E8)                                                     */
/*       BDX (0x400336E8)                                                     */
/* Register default value on IVT_EP:    0x0007BDEF                            */
/* Register default value on IVT_EX:    0x0007BDEF                            */
/* Register default value on HSX:       0x0005AD6B                            */
/* Register default value on BDX:       0x0005AD6B                            */
#define RX_VREF_SEL_GEN1_2_IIO_DFX_REG 0x120046E8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6e8
 */
typedef union {
  struct {
    UINT32 lane12 : 5;
    /* lane12 - Bits[4:0], RWS_L, default = 5'b01011  */
    UINT32 lane13 : 5;
    /* lane13 - Bits[9:5], RWS_L, default = 5'b01011  */
    UINT32 lane14 : 5;
    /* lane14 - Bits[14:10], RWS_L, default = 5'b01011  */
    UINT32 lane15 : 5;
    /* lane15 - Bits[19:15], RWS_L, default = 5'b01011  */
    UINT32 rsvd : 12;
    /* rsvd - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_VREF_SEL_GEN1_2_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_VREF_SEL_NOTGEN1_0_IIO_DFX_REG supported on:                            */
/*       IVT_EP (0x400336EC)                                                  */
/*       IVT_EX (0x400336EC)                                                  */
/*       HSX (0x400336EC)                                                     */
/*       BDX (0x400336EC)                                                     */
/* Register default value:              0x10842108                            */
#define RX_VREF_SEL_NOTGEN1_0_IIO_DFX_REG 0x120046EC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6ec
 */
typedef union {
  struct {
    UINT32 lane0 : 5;
    /* lane0 - Bits[4:0], RWS_L, default = 5'b01000  */
    UINT32 lane1 : 5;
    /* lane1 - Bits[9:5], RWS_L, default = 5'b01000  */
    UINT32 lane2 : 5;
    /* lane2 - Bits[14:10], RWS_L, default = 5'b01000  */
    UINT32 lane3 : 5;
    /* lane3 - Bits[19:15], RWS_L, default = 5'b01000  */
    UINT32 lane4 : 5;
    /* lane4 - Bits[24:20], RWS_L, default = 5'b01000  */
    UINT32 lane5 : 5;
    /* lane5 - Bits[29:25], RWS_L, default = 5'b01000  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_VREF_SEL_NOTGEN1_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_VREF_SEL_NOTGEN1_1_IIO_DFX_REG supported on:                            */
/*       IVT_EP (0x400336F0)                                                  */
/*       IVT_EX (0x400336F0)                                                  */
/*       HSX (0x400336F0)                                                     */
/*       BDX (0x400336F0)                                                     */
/* Register default value:              0x10842108                            */
#define RX_VREF_SEL_NOTGEN1_1_IIO_DFX_REG 0x120046F0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6f0
 */
typedef union {
  struct {
    UINT32 lane6 : 5;
    /* lane6 - Bits[4:0], RWS_L, default = 5'b01000  */
    UINT32 lane7 : 5;
    /* lane7 - Bits[9:5], RWS_L, default = 5'b01000  */
    UINT32 lane8 : 5;
    /* lane8 - Bits[14:10], RWS_L, default = 5'b01000  */
    UINT32 lane9 : 5;
    /* lane9 - Bits[19:15], RWS_L, default = 5'b01000  */
    UINT32 lane10 : 5;
    /* lane10 - Bits[24:20], RWS_L, default = 5'b01000  */
    UINT32 lane11 : 5;
    /* lane11 - Bits[29:25], RWS_L, default = 5'b01000  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_VREF_SEL_NOTGEN1_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_VREF_SEL_NOTGEN1_2_IIO_DFX_REG supported on:                            */
/*       IVT_EP (0x400336F4)                                                  */
/*       IVT_EX (0x400336F4)                                                  */
/*       HSX (0x400336F4)                                                     */
/*       BDX (0x400336F4)                                                     */
/* Register default value:              0x00042108                            */
#define RX_VREF_SEL_NOTGEN1_2_IIO_DFX_REG 0x120046F4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x6f4
 */
typedef union {
  struct {
    UINT32 lane12 : 5;
    /* lane12 - Bits[4:0], RWS_L, default = 5'b01000  */
    UINT32 lane13 : 5;
    /* lane13 - Bits[9:5], RWS_L, default = 5'b01000  */
    UINT32 lane14 : 5;
    /* lane14 - Bits[14:10], RWS_L, default = 5'b01000  */
    UINT32 lane15 : 5;
    /* lane15 - Bits[19:15], RWS_L, default = 5'b01000  */
    UINT32 rsvd : 12;
    /* rsvd - Bits[31:20], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_VREF_SEL_NOTGEN1_2_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* IG_ACQ_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x40033700)                                                  */
/*       IVT_EX (0x40033700)                                                  */
/*       HSX (0x40033700)                                                     */
/*       BDX (0x40033700)                                                     */
/* Register default value:              0x00000000                            */
#define IG_ACQ_IIO_DFX_REG 0x12004700
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x700
 */
typedef union {
  struct {
    UINT32 bndl0 : 3;
    /* bndl0 - Bits[2:0], RWS_L, default = 3'b000  */
    UINT32 bndl1 : 3;
    /* bndl1 - Bits[5:3], RWS_L, default = 3'b000  */
    UINT32 bndl2 : 3;
    /* bndl2 - Bits[8:6], RWS_L, default = 3'b000  */
    UINT32 bndl3 : 3;
    /* bndl3 - Bits[11:9], RWS_L, default = 3'b000  */
    UINT32 bndl4 : 3;
    /* bndl4 - Bits[14:12], RWS_L, default = 3'b000  */
    UINT32 bndl5 : 3;
    /* bndl5 - Bits[17:15], RWS_L, default = 3'b000  */
    UINT32 bndl6 : 3;
    /* bndl6 - Bits[20:18], RWS_L, default = 3'b000  */
    UINT32 bndl7 : 3;
    /* bndl7 - Bits[23:21], RWS_L, default = 3'b000  */
    UINT32 rsvd : 8;
    /* rsvd - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IG_ACQ_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* IG_TRACK_IIO_DFX_REG supported on:                                         */
/*       IVT_EP (0x40033704)                                                  */
/*       IVT_EX (0x40033704)                                                  */
/*       HSX (0x40033704)                                                     */
/*       BDX (0x40033704)                                                     */
/* Register default value:              0x00492492                            */
#define IG_TRACK_IIO_DFX_REG 0x12004704
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x704
 */
typedef union {
  struct {
    UINT32 bndl0 : 3;
    /* bndl0 - Bits[2:0], RWS_L, default = 3'b010  */
    UINT32 bndl1 : 3;
    /* bndl1 - Bits[5:3], RWS_L, default = 3'b010  */
    UINT32 bndl2 : 3;
    /* bndl2 - Bits[8:6], RWS_L, default = 3'b010  */
    UINT32 bndl3 : 3;
    /* bndl3 - Bits[11:9], RWS_L, default = 3'b010  */
    UINT32 bndl4 : 3;
    /* bndl4 - Bits[14:12], RWS_L, default = 3'b010  */
    UINT32 bndl5 : 3;
    /* bndl5 - Bits[17:15], RWS_L, default = 3'b010  */
    UINT32 bndl6 : 3;
    /* bndl6 - Bits[20:18], RWS_L, default = 3'b010  */
    UINT32 bndl7 : 3;
    /* bndl7 - Bits[23:21], RWS_L, default = 3'b010  */
    UINT32 rsvd : 8;
    /* rsvd - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} IG_TRACK_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PG_ACQ_0_IIO_DFX_REG supported on:                                         */
/*       IVT_EP (0x40033708)                                                  */
/*       IVT_EX (0x40033708)                                                  */
/*       HSX (0x40033708)                                                     */
/*       BDX (0x40033708)                                                     */
/* Register default value:              0x10410410                            */
#define PG_ACQ_0_IIO_DFX_REG 0x12004708
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x708
 */
typedef union {
  struct {
    UINT32 bndl0 : 6;
    /* bndl0 - Bits[5:0], RWS_L, default = 6'b010000  */
    UINT32 bndl1 : 6;
    /* bndl1 - Bits[11:6], RWS_L, default = 6'b010000  */
    UINT32 bndl2 : 6;
    /* bndl2 - Bits[17:12], RWS_L, default = 6'b010000  */
    UINT32 bndl3 : 6;
    /* bndl3 - Bits[23:18], RWS_L, default = 6'b010000  */
    UINT32 bndl4 : 6;
    /* bndl4 - Bits[29:24], RWS_L, default = 6'b010000  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PG_ACQ_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PG_ACQ_1_IIO_DFX_REG supported on:                                         */
/*       IVT_EP (0x4003370C)                                                  */
/*       IVT_EX (0x4003370C)                                                  */
/*       HSX (0x4003370C)                                                     */
/*       BDX (0x4003370C)                                                     */
/* Register default value:              0x00010410                            */
#define PG_ACQ_1_IIO_DFX_REG 0x1200470C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x70c
 */
typedef union {
  struct {
    UINT32 bndl5 : 6;
    /* bndl5 - Bits[5:0], RWS_L, default = 6'b010000  */
    UINT32 bndl6 : 6;
    /* bndl6 - Bits[11:6], RWS_L, default = 6'b010000  */
    UINT32 bndl7 : 6;
    /* bndl7 - Bits[17:12], RWS_L, default = 6'b010000  */
    UINT32 rsvd : 14;
    /* rsvd - Bits[31:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PG_ACQ_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PG_TRACK_0_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x40033710)                                                  */
/*       IVT_EX (0x40033710)                                                  */
/*       HSX (0x40033710)                                                     */
/*       BDX (0x40033710)                                                     */
/* Register default value:              0x0A28A28A                            */
#define PG_TRACK_0_IIO_DFX_REG 0x12004710
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x710
 */
typedef union {
  struct {
    UINT32 bndl0 : 6;
    /* bndl0 - Bits[5:0], RWS_L, default = 6'b001010  */
    UINT32 bndl1 : 6;
    /* bndl1 - Bits[11:6], RWS_L, default = 6'b001010  */
    UINT32 bndl2 : 6;
    /* bndl2 - Bits[17:12], RWS_L, default = 6'b001010  */
    UINT32 bndl3 : 6;
    /* bndl3 - Bits[23:18], RWS_L, default = 6'b001010  */
    UINT32 bndl4 : 6;
    /* bndl4 - Bits[29:24], RWS_L, default = 6'b001010  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PG_TRACK_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PG_TRACK_1_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x40033714)                                                  */
/*       IVT_EX (0x40033714)                                                  */
/*       HSX (0x40033714)                                                     */
/*       BDX (0x40033714)                                                     */
/* Register default value:              0x0000A28A                            */
#define PG_TRACK_1_IIO_DFX_REG 0x12004714
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x714
 */
typedef union {
  struct {
    UINT32 bndl5 : 6;
    /* bndl5 - Bits[5:0], RWS_L, default = 6'b001010  */
    UINT32 bndl6 : 6;
    /* bndl6 - Bits[11:6], RWS_L, default = 6'b001010  */
    UINT32 bndl7 : 6;
    /* bndl7 - Bits[17:12], RWS_L, default = 6'b001010  */
    UINT32 rsvd : 14;
    /* rsvd - Bits[31:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PG_TRACK_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_PDTC_IIO_DFX_REG supported on:                                         */
/*       IVT_EP (0x40033718)                                                  */
/*       IVT_EX (0x40033718)                                                  */
/*       HSX (0x40033718)                                                     */
/*       BDX (0x40033718)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_PDTC_IIO_DFX_REG 0x12004718
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x718
 */
typedef union {
  struct {
    UINT32 lane0 : 2;
    /* lane0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 lane1 : 2;
    /* lane1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 lane2 : 2;
    /* lane2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 lane3 : 2;
    /* lane3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 lane4 : 2;
    /* lane4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 lane5 : 2;
    /* lane5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 lane6 : 2;
    /* lane6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 lane7 : 2;
    /* lane7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 lane8 : 2;
    /* lane8 - Bits[17:16], RWS_L, default = 2'b00  */
    UINT32 lane9 : 2;
    /* lane9 - Bits[19:18], RWS_L, default = 2'b00  */
    UINT32 lane10 : 2;
    /* lane10 - Bits[21:20], RWS_L, default = 2'b00  */
    UINT32 lane11 : 2;
    /* lane11 - Bits[23:22], RWS_L, default = 2'b00  */
    UINT32 lane12 : 2;
    /* lane12 - Bits[25:24], RWS_L, default = 2'b00  */
    UINT32 lane13 : 2;
    /* lane13 - Bits[27:26], RWS_L, default = 2'b00  */
    UINT32 lane14 : 2;
    /* lane14 - Bits[29:28], RWS_L, default = 2'b00  */
    UINT32 lane15 : 2;
    /* lane15 - Bits[31:30], RWS_L, default = 2'b00  */
  } Bits;
  UINT32 Data;
} CDR_PDTC_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_FORCE_ACQ_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x40033720)                                                  */
/*       IVT_EX (0x40033720)                                                  */
/*       HSX (0x40033720)                                                     */
/*       BDX (0x40033720)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_FORCE_ACQ_IIO_DFX_REG 0x12004720
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x720
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CDR_FORCE_ACQ_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_PD_DATAMODE_IIO_DFX_REG supported on:                                  */
/*       IVT_EP (0x40033724)                                                  */
/*       IVT_EX (0x40033724)                                                  */
/*       HSX (0x40033724)                                                     */
/*       BDX (0x40033724)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_PD_DATAMODE_IIO_DFX_REG 0x12004724
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x724
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CDR_PD_DATAMODE_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_PD_MODE_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x40033728)                                                  */
/*       IVT_EX (0x40033728)                                                  */
/*       HSX (0x40033728)                                                     */
/*       BDX (0x40033728)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_PD_MODE_IIO_DFX_REG 0x12004728
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x728
 */
typedef union {
  struct {
    UINT32 lane0 : 2;
    /* lane0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 lane1 : 2;
    /* lane1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 lane2 : 2;
    /* lane2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 lane3 : 2;
    /* lane3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 lane4 : 2;
    /* lane4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 lane5 : 2;
    /* lane5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 lane6 : 2;
    /* lane6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 lane7 : 2;
    /* lane7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 lane8 : 2;
    /* lane8 - Bits[17:16], RWS_L, default = 2'b00  */
    UINT32 lane9 : 2;
    /* lane9 - Bits[19:18], RWS_L, default = 2'b00  */
    UINT32 lane10 : 2;
    /* lane10 - Bits[21:20], RWS_L, default = 2'b00  */
    UINT32 lane11 : 2;
    /* lane11 - Bits[23:22], RWS_L, default = 2'b00  */
    UINT32 lane12 : 2;
    /* lane12 - Bits[25:24], RWS_L, default = 2'b00  */
    UINT32 lane13 : 2;
    /* lane13 - Bits[27:26], RWS_L, default = 2'b00  */
    UINT32 lane14 : 2;
    /* lane14 - Bits[29:28], RWS_L, default = 2'b00  */
    UINT32 lane15 : 2;
    /* lane15 - Bits[31:30], RWS_L, default = 2'b00  */
  } Bits;
  UINT32 Data;
} CDR_PD_MODE_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_PPM_OFFSET_EN_IIO_DFX_REG supported on:                                */
/*       IVT_EP (0x40033730)                                                  */
/*       IVT_EX (0x40033730)                                                  */
/*       HSX (0x40033730)                                                     */
/*       BDX (0x40033730)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_PPM_OFFSET_EN_IIO_DFX_REG 0x12004730
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x730
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CDR_PPM_OFFSET_EN_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_PPM_OFFSET_0_IIO_DFX_REG supported on:                                 */
/*       IVT_EP (0x40033734)                                                  */
/*       IVT_EX (0x40033734)                                                  */
/*       HSX (0x40033734)                                                     */
/*       BDX (0x40033734)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_PPM_OFFSET_0_IIO_DFX_REG 0x12004734
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x734
 */
typedef union {
  struct {
    UINT32 bndl0 : 7;
    /* bndl0 - Bits[6:0], RWS_L, default = 7'b0000000  */
    UINT32 bndl1 : 7;
    /* bndl1 - Bits[13:7], RWS_L, default = 7'b0000000  */
    UINT32 bndl2 : 7;
    /* bndl2 - Bits[20:14], RWS_L, default = 7'b0000000  */
    UINT32 bndl3 : 7;
    /* bndl3 - Bits[27:21], RWS_L, default = 7'b0000000  */
    UINT32 rsvd : 4;
    /* rsvd - Bits[31:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CDR_PPM_OFFSET_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_PPM_OFFSET_1_IIO_DFX_REG supported on:                                 */
/*       IVT_EP (0x40033738)                                                  */
/*       IVT_EX (0x40033738)                                                  */
/*       HSX (0x40033738)                                                     */
/*       BDX (0x40033738)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_PPM_OFFSET_1_IIO_DFX_REG 0x12004738
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x738
 */
typedef union {
  struct {
    UINT32 bndl4 : 7;
    /* bndl4 - Bits[6:0], RWS_L, default = 7'b0000000  */
    UINT32 bndl5 : 7;
    /* bndl5 - Bits[13:7], RWS_L, default = 7'b0000000  */
    UINT32 bndl6 : 7;
    /* bndl6 - Bits[20:14], RWS_L, default = 7'b0000000  */
    UINT32 bndl7 : 7;
    /* bndl7 - Bits[27:21], RWS_L, default = 7'b0000000  */
    UINT32 rsvd : 4;
    /* rsvd - Bits[31:28], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CDR_PPM_OFFSET_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_PMOD_EN_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x40033744)                                                  */
/*       IVT_EX (0x40033744)                                                  */
/*       HSX (0x40033744)                                                     */
/*       BDX (0x40033744)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_PMOD_EN_IIO_DFX_REG 0x12004744
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x744
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CDR_PMOD_EN_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_PMOD_STEP_0_IIO_DFX_REG supported on:                                  */
/*       IVT_EP (0x40033748)                                                  */
/*       IVT_EX (0x40033748)                                                  */
/*       HSX (0x40033748)                                                     */
/*       BDX (0x40033748)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_PMOD_STEP_0_IIO_DFX_REG 0x12004748
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x748
 */
typedef union {
  struct {
    UINT32 bndl0 : 8;
    /* bndl0 - Bits[7:0], RWS_L, default = 8'b00000000  */
    UINT32 bndl1 : 8;
    /* bndl1 - Bits[15:8], RWS_L, default = 8'b00000000  */
    UINT32 bndl2 : 8;
    /* bndl2 - Bits[23:16], RWS_L, default = 8'b00000000  */
    UINT32 bndl3 : 8;
    /* bndl3 - Bits[31:24], RWS_L, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} CDR_PMOD_STEP_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_PMOD_STEP_1_IIO_DFX_REG supported on:                                  */
/*       IVT_EP (0x4003374C)                                                  */
/*       IVT_EX (0x4003374C)                                                  */
/*       HSX (0x4003374C)                                                     */
/*       BDX (0x4003374C)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_PMOD_STEP_1_IIO_DFX_REG 0x1200474C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x74c
 */
typedef union {
  struct {
    UINT32 bndl4 : 8;
    /* bndl4 - Bits[7:0], RWS_L, default = 8'b00000000  */
    UINT32 bndl5 : 8;
    /* bndl5 - Bits[15:8], RWS_L, default = 8'b00000000  */
    UINT32 bndl6 : 8;
    /* bndl6 - Bits[23:16], RWS_L, default = 8'b00000000  */
    UINT32 bndl7 : 8;
    /* bndl7 - Bits[31:24], RWS_L, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} CDR_PMOD_STEP_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_PMOD_PEAK_0_IIO_DFX_REG supported on:                                  */
/*       IVT_EP (0x40033758)                                                  */
/*       IVT_EX (0x40033758)                                                  */
/*       HSX (0x40033758)                                                     */
/*       BDX (0x40033758)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_PMOD_PEAK_0_IIO_DFX_REG 0x12004758
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x758
 */
typedef union {
  struct {
    UINT32 bndl0 : 6;
    /* bndl0 - Bits[5:0], RWS_L, default = 6'b000000  */
    UINT32 bndl1 : 6;
    /* bndl1 - Bits[11:6], RWS_L, default = 6'b000000  */
    UINT32 bndl2 : 6;
    /* bndl2 - Bits[17:12], RWS_L, default = 6'b000000  */
    UINT32 bndl3 : 6;
    /* bndl3 - Bits[23:18], RWS_L, default = 6'b000000  */
    UINT32 bndl4 : 6;
    /* bndl4 - Bits[29:24], RWS_L, default = 6'b000000  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CDR_PMOD_PEAK_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_PMOD_PEAK_1_IIO_DFX_REG supported on:                                  */
/*       IVT_EP (0x4003375C)                                                  */
/*       IVT_EX (0x4003375C)                                                  */
/*       HSX (0x4003375C)                                                     */
/*       BDX (0x4003375C)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_PMOD_PEAK_1_IIO_DFX_REG 0x1200475C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x75c
 */
typedef union {
  struct {
    UINT32 bndl5 : 6;
    /* bndl5 - Bits[5:0], RWS_L, default = 6'b000000  */
    UINT32 bndl6 : 6;
    /* bndl6 - Bits[11:6], RWS_L, default = 6'b000000  */
    UINT32 bndl7 : 6;
    /* bndl7 - Bits[17:12], RWS_L, default = 6'b000000  */
    UINT32 rsvd : 14;
    /* rsvd - Bits[31:18], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CDR_PMOD_PEAK_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_ACQ_LENGTH_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x40033760)                                                  */
/*       IVT_EX (0x40033760)                                                  */
/*       HSX (0x40033760)                                                     */
/*       BDX (0x40033760)                                                     */
/* Register default value:              0x55555555                            */
#define CDR_ACQ_LENGTH_IIO_DFX_REG 0x12004760
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x760
 */
typedef union {
  struct {
    UINT32 lane0 : 2;
    /* lane0 - Bits[1:0], RWS_L, default = 2'b01  */
    UINT32 lane1 : 2;
    /* lane1 - Bits[3:2], RWS_L, default = 2'b01  */
    UINT32 lane2 : 2;
    /* lane2 - Bits[5:4], RWS_L, default = 2'b01  */
    UINT32 lane3 : 2;
    /* lane3 - Bits[7:6], RWS_L, default = 2'b01  */
    UINT32 lane4 : 2;
    /* lane4 - Bits[9:8], RWS_L, default = 2'b01  */
    UINT32 lane5 : 2;
    /* lane5 - Bits[11:10], RWS_L, default = 2'b01  */
    UINT32 lane6 : 2;
    /* lane6 - Bits[13:12], RWS_L, default = 2'b01  */
    UINT32 lane7 : 2;
    /* lane7 - Bits[15:14], RWS_L, default = 2'b01  */
    UINT32 lane8 : 2;
    /* lane8 - Bits[17:16], RWS_L, default = 2'b01  */
    UINT32 lane9 : 2;
    /* lane9 - Bits[19:18], RWS_L, default = 2'b01  */
    UINT32 lane10 : 2;
    /* lane10 - Bits[21:20], RWS_L, default = 2'b01  */
    UINT32 lane11 : 2;
    /* lane11 - Bits[23:22], RWS_L, default = 2'b01  */
    UINT32 lane12 : 2;
    /* lane12 - Bits[25:24], RWS_L, default = 2'b01  */
    UINT32 lane13 : 2;
    /* lane13 - Bits[27:26], RWS_L, default = 2'b01  */
    UINT32 lane14 : 2;
    /* lane14 - Bits[29:28], RWS_L, default = 2'b01  */
    UINT32 lane15 : 2;
    /* lane15 - Bits[31:30], RWS_L, default = 2'b01  */
  } Bits;
  UINT32 Data;
} CDR_ACQ_LENGTH_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_BNDL_MODE_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x40033768)                                                  */
/*       IVT_EX (0x40033768)                                                  */
/*       HSX (0x40033768)                                                     */
/*       BDX (0x40033768)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_BNDL_MODE_IIO_DFX_REG 0x12004768
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x768
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CDR_BNDL_MODE_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* CDR_OPEN_LOOP_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x4003376C)                                                  */
/*       IVT_EX (0x4003376C)                                                  */
/*       HSX (0x4003376C)                                                     */
/*       BDX (0x4003376C)                                                     */
/* Register default value:              0x00000000                            */
#define CDR_OPEN_LOOP_IIO_DFX_REG 0x1200476C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x76c
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} CDR_OPEN_LOOP_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* AGC_OPEN_LOOP_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x40033770)                                                  */
/*       IVT_EX (0x40033770)                                                  */
/*       HSX (0x40033770)                                                     */
/*       BDX (0x40033770)                                                     */
/* Register default value:              0x00000000                            */
#define AGC_OPEN_LOOP_IIO_DFX_REG 0x12004770
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x770
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} AGC_OPEN_LOOP_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* AGC_FORCE_ACQ_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x40033774)                                                  */
/*       IVT_EX (0x40033774)                                                  */
/*       HSX (0x40033774)                                                     */
/*       BDX (0x40033774)                                                     */
/* Register default value:              0x00000000                            */
#define AGC_FORCE_ACQ_IIO_DFX_REG 0x12004774
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x774
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} AGC_FORCE_ACQ_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* AGC_UPDATE_RATE_ACQ_IIO_DFX_REG supported on:                              */
/*       IVT_EP (0x40033778)                                                  */
/*       IVT_EX (0x40033778)                                                  */
/*       HSX (0x40033778)                                                     */
/*       BDX (0x40033778)                                                     */
/* Register default value:              0x00000000                            */
#define AGC_UPDATE_RATE_ACQ_IIO_DFX_REG 0x12004778
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x778
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} AGC_UPDATE_RATE_ACQ_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* AGC_UPDATE_RATE_TRACK_IIO_DFX_REG supported on:                            */
/*       IVT_EP (0x4003377C)                                                  */
/*       IVT_EX (0x4003377C)                                                  */
/*       HSX (0x4003377C)                                                     */
/*       BDX (0x4003377C)                                                     */
/* Register default value:              0x00000000                            */
#define AGC_UPDATE_RATE_TRACK_IIO_DFX_REG 0x1200477C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x77c
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} AGC_UPDATE_RATE_TRACK_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* AGC_GAIN_ACQ_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x40033780)                                                  */
/*       IVT_EX (0x40033780)                                                  */
/*       HSX (0x40033780)                                                     */
/*       BDX (0x40033780)                                                     */
/* Register default value:              0x0000FFFF                            */
#define AGC_GAIN_ACQ_IIO_DFX_REG 0x12004780
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x780
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b11  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b11  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b11  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b11  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b11  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b11  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b11  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b11  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} AGC_GAIN_ACQ_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* AGC_GAIN_TRACK_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x40033784)                                                  */
/*       IVT_EX (0x40033784)                                                  */
/*       HSX (0x40033784)                                                     */
/*       BDX (0x40033784)                                                     */
/* Register default value:              0x00000000                            */
#define AGC_GAIN_TRACK_IIO_DFX_REG 0x12004784
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x784
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} AGC_GAIN_TRACK_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* AGC_ACQ_LENGTH_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x40033788)                                                  */
/*       IVT_EX (0x40033788)                                                  */
/*       HSX (0x40033788)                                                     */
/*       BDX (0x40033788)                                                     */
/* Register default value:              0xAAAAAAAA                            */
#define AGC_ACQ_LENGTH_IIO_DFX_REG 0x12004788
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x788
 */
typedef union {
  struct {
    UINT32 lane0 : 2;
    /* lane0 - Bits[1:0], RWS_L, default = 2'b10  */
    UINT32 lane1 : 2;
    /* lane1 - Bits[3:2], RWS_L, default = 2'b10  */
    UINT32 lane2 : 2;
    /* lane2 - Bits[5:4], RWS_L, default = 2'b10  */
    UINT32 lane3 : 2;
    /* lane3 - Bits[7:6], RWS_L, default = 2'b10  */
    UINT32 lane4 : 2;
    /* lane4 - Bits[9:8], RWS_L, default = 2'b10  */
    UINT32 lane5 : 2;
    /* lane5 - Bits[11:10], RWS_L, default = 2'b10  */
    UINT32 lane6 : 2;
    /* lane6 - Bits[13:12], RWS_L, default = 2'b10  */
    UINT32 lane7 : 2;
    /* lane7 - Bits[15:14], RWS_L, default = 2'b10  */
    UINT32 lane8 : 2;
    /* lane8 - Bits[17:16], RWS_L, default = 2'b10  */
    UINT32 lane9 : 2;
    /* lane9 - Bits[19:18], RWS_L, default = 2'b10  */
    UINT32 lane10 : 2;
    /* lane10 - Bits[21:20], RWS_L, default = 2'b10  */
    UINT32 lane11 : 2;
    /* lane11 - Bits[23:22], RWS_L, default = 2'b10  */
    UINT32 lane12 : 2;
    /* lane12 - Bits[25:24], RWS_L, default = 2'b10  */
    UINT32 lane13 : 2;
    /* lane13 - Bits[27:26], RWS_L, default = 2'b10  */
    UINT32 lane14 : 2;
    /* lane14 - Bits[29:28], RWS_L, default = 2'b10  */
    UINT32 lane15 : 2;
    /* lane15 - Bits[31:30], RWS_L, default = 2'b10  */
  } Bits;
  UINT32 Data;
} AGC_ACQ_LENGTH_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_AGC_USE_ERR_DATA_IIO_DFX_REG supported on:                              */
/*       IVT_EP (0x40033790)                                                  */
/*       IVT_EX (0x40033790)                                                  */
/*       HSX (0x40033790)                                                     */
/*       BDX (0x40033790)                                                     */
/* Register default value:              0x0000FFFF                            */
#define RX_AGC_USE_ERR_DATA_IIO_DFX_REG 0x12004790
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x790
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b1  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b1  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b1  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b1  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b1  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b1  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b1  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b1  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b1  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b1  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b1  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_AGC_USE_ERR_DATA_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DFE_FORCE_ACQ_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x40033794)                                                  */
/*       IVT_EX (0x40033794)                                                  */
/*       HSX (0x40033794)                                                     */
/*       BDX (0x40033794)                                                     */
/* Register default value:              0x00000000                            */
#define DFE_FORCE_ACQ_IIO_DFX_REG 0x12004794
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x794
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DFE_FORCE_ACQ_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DFE_GAIN_ACQ_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x40033798)                                                  */
/*       IVT_EX (0x40033798)                                                  */
/*       HSX (0x40033798)                                                     */
/*       BDX (0x40033798)                                                     */
/* Register default value:              0x0000FFFF                            */
#define DFE_GAIN_ACQ_IIO_DFX_REG 0x12004798
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x798
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b11  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b11  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b11  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b11  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b11  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b11  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b11  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b11  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DFE_GAIN_ACQ_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DFE_GAIN_TRACK_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x4003379C)                                                  */
/*       IVT_EX (0x4003379C)                                                  */
/*       HSX (0x4003379C)                                                     */
/*       BDX (0x4003379C)                                                     */
/* Register default value:              0x00000000                            */
#define DFE_GAIN_TRACK_IIO_DFX_REG 0x1200479C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x79c
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DFE_GAIN_TRACK_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DFE_OPEN_LOOP_TAP_0_IIO_DFX_REG supported on:                              */
/*       IVT_EP (0x400337A0)                                                  */
/*       IVT_EX (0x400337A0)                                                  */
/*       HSX (0x400337A0)                                                     */
/*       BDX (0x400337A0)                                                     */
/* Register default value:              0x00000000                            */
#define DFE_OPEN_LOOP_TAP_0_IIO_DFX_REG 0x120047A0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x7a0
 */
typedef union {
  struct {
    UINT32 lane0 : 4;
    /* lane0 - Bits[3:0], RWS_L, default = 4'b0000  */
    UINT32 lane1 : 4;
    /* lane1 - Bits[7:4], RWS_L, default = 4'b0000  */
    UINT32 lane2 : 4;
    /* lane2 - Bits[11:8], RWS_L, default = 4'b0000  */
    UINT32 lane3 : 4;
    /* lane3 - Bits[15:12], RWS_L, default = 4'b0000  */
    UINT32 lane4 : 4;
    /* lane4 - Bits[19:16], RWS_L, default = 4'b0000  */
    UINT32 lane5 : 4;
    /* lane5 - Bits[23:20], RWS_L, default = 4'b0000  */
    UINT32 lane6 : 4;
    /* lane6 - Bits[27:24], RWS_L, default = 4'b0000  */
    UINT32 lane7 : 4;
    /* lane7 - Bits[31:28], RWS_L, default = 4'b0000  */
  } Bits;
  UINT32 Data;
} DFE_OPEN_LOOP_TAP_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DFE_OPEN_LOOP_TAP_1_IIO_DFX_REG supported on:                              */
/*       IVT_EP (0x400337A4)                                                  */
/*       IVT_EX (0x400337A4)                                                  */
/*       HSX (0x400337A4)                                                     */
/*       BDX (0x400337A4)                                                     */
/* Register default value:              0x00000000                            */
#define DFE_OPEN_LOOP_TAP_1_IIO_DFX_REG 0x120047A4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x7a4
 */
typedef union {
  struct {
    UINT32 lane8 : 4;
    /* lane8 - Bits[3:0], RWS_L, default = 4'b0000  */
    UINT32 lane9 : 4;
    /* lane9 - Bits[7:4], RWS_L, default = 4'b0000  */
    UINT32 lane10 : 4;
    /* lane10 - Bits[11:8], RWS_L, default = 4'b0000  */
    UINT32 lane11 : 4;
    /* lane11 - Bits[15:12], RWS_L, default = 4'b0000  */
    UINT32 lane12 : 4;
    /* lane12 - Bits[19:16], RWS_L, default = 4'b0000  */
    UINT32 lane13 : 4;
    /* lane13 - Bits[23:20], RWS_L, default = 4'b0000  */
    UINT32 lane14 : 4;
    /* lane14 - Bits[27:24], RWS_L, default = 4'b0000  */
    UINT32 lane15 : 4;
    /* lane15 - Bits[31:28], RWS_L, default = 4'b0000  */
  } Bits;
  UINT32 Data;
} DFE_OPEN_LOOP_TAP_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DFE_ACQ_LENGTH_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x400337B0)                                                  */
/*       IVT_EX (0x400337B0)                                                  */
/*       HSX (0x400337B0)                                                     */
/*       BDX (0x400337B0)                                                     */
/* Register default value:              0xFFFFFFFF                            */
#define DFE_ACQ_LENGTH_IIO_DFX_REG 0x120047B0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x7b0
 */
typedef union {
  struct {
    UINT32 lane0 : 2;
    /* lane0 - Bits[1:0], RWS_L, default = 2'b11  */
    UINT32 lane1 : 2;
    /* lane1 - Bits[3:2], RWS_L, default = 2'b11  */
    UINT32 lane2 : 2;
    /* lane2 - Bits[5:4], RWS_L, default = 2'b11  */
    UINT32 lane3 : 2;
    /* lane3 - Bits[7:6], RWS_L, default = 2'b11  */
    UINT32 lane4 : 2;
    /* lane4 - Bits[9:8], RWS_L, default = 2'b11  */
    UINT32 lane5 : 2;
    /* lane5 - Bits[11:10], RWS_L, default = 2'b11  */
    UINT32 lane6 : 2;
    /* lane6 - Bits[13:12], RWS_L, default = 2'b11  */
    UINT32 lane7 : 2;
    /* lane7 - Bits[15:14], RWS_L, default = 2'b11  */
    UINT32 lane8 : 2;
    /* lane8 - Bits[17:16], RWS_L, default = 2'b11  */
    UINT32 lane9 : 2;
    /* lane9 - Bits[19:18], RWS_L, default = 2'b11  */
    UINT32 lane10 : 2;
    /* lane10 - Bits[21:20], RWS_L, default = 2'b11  */
    UINT32 lane11 : 2;
    /* lane11 - Bits[23:22], RWS_L, default = 2'b11  */
    UINT32 lane12 : 2;
    /* lane12 - Bits[25:24], RWS_L, default = 2'b11  */
    UINT32 lane13 : 2;
    /* lane13 - Bits[27:26], RWS_L, default = 2'b11  */
    UINT32 lane14 : 2;
    /* lane14 - Bits[29:28], RWS_L, default = 2'b11  */
    UINT32 lane15 : 2;
    /* lane15 - Bits[31:30], RWS_L, default = 2'b11  */
  } Bits;
  UINT32 Data;
} DFE_ACQ_LENGTH_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DFE_UPDATE_RATE_ACQ_IIO_DFX_REG supported on:                              */
/*       IVT_EP (0x400337B8)                                                  */
/*       IVT_EX (0x400337B8)                                                  */
/*       HSX (0x400337B8)                                                     */
/*       BDX (0x400337B8)                                                     */
/* Register default value:              0x00000000                            */
#define DFE_UPDATE_RATE_ACQ_IIO_DFX_REG 0x120047B8
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x7b8
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DFE_UPDATE_RATE_ACQ_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DFE_UPDATE_RATE_TRACK_IIO_DFX_REG supported on:                            */
/*       IVT_EP (0x400337BC)                                                  */
/*       IVT_EX (0x400337BC)                                                  */
/*       HSX (0x400337BC)                                                     */
/*       BDX (0x400337BC)                                                     */
/* Register default value:              0x0000AAAA                            */
#define DFE_UPDATE_RATE_TRACK_IIO_DFX_REG 0x120047BC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x7bc
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b10  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b10  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b10  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b10  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b10  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b10  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b10  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b10  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DFE_UPDATE_RATE_TRACK_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* WSEL_IIO_DFX_REG supported on:                                             */
/*       HSX (0x400337C0)                                                     */
/*       BDX (0x400337C0)                                                     */
/* Register default value:              0x00B6DB6D                            */
#define WSEL_IIO_DFX_REG 0x120047C0

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x7c0
 */
typedef union {
  struct {
    UINT32 bndl0 : 3;
    /* bndl0 - Bits[2:0], RWS_L, default = 3'b101  */
    UINT32 bndl1 : 3;
    /* bndl1 - Bits[5:3], RWS_L, default = 3'b101  */
    UINT32 bndl2 : 3;
    /* bndl2 - Bits[8:6], RWS_L, default = 3'b101  */
    UINT32 bndl3 : 3;
    /* bndl3 - Bits[11:9], RWS_L, default = 3'b101  */
    UINT32 bndl4 : 3;
    /* bndl4 - Bits[14:12], RWS_L, default = 3'b101  */
    UINT32 bndl5 : 3;
    /* bndl5 - Bits[17:15], RWS_L, default = 3'b101  */
    UINT32 bndl6 : 3;
    /* bndl6 - Bits[20:18], RWS_L, default = 3'b101  */
    UINT32 bndl7 : 3;
    /* bndl7 - Bits[23:21], RWS_L, default = 3'b101  */
    UINT32 rsvd : 8;
    /* rsvd - Bits[31:24], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} WSEL_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* VOTECNT_IIO_DFX_REG supported on:                                          */
/*       HSX (0x400337C4)                                                     */
/*       BDX (0x400337C4)                                                     */
/* Register default value:              0x00005555                            */
#define VOTECNT_IIO_DFX_REG 0x120047C4

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x7c4
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b01  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b01  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b01  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b01  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b01  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b01  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b01  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b01  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} VOTECNT_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* TX_RTERM_DIS_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x400337D0)                                                  */
/*       IVT_EX (0x400337D0)                                                  */
/*       HSX (0x400337D0)                                                     */
/*       BDX (0x400337D0)                                                     */
/* Register default value:              0x00000000                            */
#define TX_RTERM_DIS_IIO_DFX_REG 0x120047D0
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x7d0
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_RTERM_DIS_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_RTERM_PULLHIGH_N_IIO_DFX_REG supported on:                              */
/*       IVT_EP (0x400337D4)                                                  */
/*       IVT_EX (0x400337D4)                                                  */
/*       HSX (0x400337D4)                                                     */
/*       BDX (0x400337D4)                                                     */
/* Register default value:              0xFFFFFFFF                            */
#define TX_RTERM_PULLHIGH_N_IIO_DFX_REG 0x120047D4
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x7d4
 */
typedef union {
  struct {
    UINT32 lane0 : 2;
    /* lane0 - Bits[1:0], RWS_L, default = 2'b11  */
    UINT32 lane1 : 2;
    /* lane1 - Bits[3:2], RWS_L, default = 2'b11  */
    UINT32 lane2 : 2;
    /* lane2 - Bits[5:4], RWS_L, default = 2'b11  */
    UINT32 lane3 : 2;
    /* lane3 - Bits[7:6], RWS_L, default = 2'b11  */
    UINT32 lane4 : 2;
    /* lane4 - Bits[9:8], RWS_L, default = 2'b11  */
    UINT32 lane5 : 2;
    /* lane5 - Bits[11:10], RWS_L, default = 2'b11  */
    UINT32 lane6 : 2;
    /* lane6 - Bits[13:12], RWS_L, default = 2'b11  */
    UINT32 lane7 : 2;
    /* lane7 - Bits[15:14], RWS_L, default = 2'b11  */
    UINT32 lane8 : 2;
    /* lane8 - Bits[17:16], RWS_L, default = 2'b11  */
    UINT32 lane9 : 2;
    /* lane9 - Bits[19:18], RWS_L, default = 2'b11  */
    UINT32 lane10 : 2;
    /* lane10 - Bits[21:20], RWS_L, default = 2'b11  */
    UINT32 lane11 : 2;
    /* lane11 - Bits[23:22], RWS_L, default = 2'b11  */
    UINT32 lane12 : 2;
    /* lane12 - Bits[25:24], RWS_L, default = 2'b11  */
    UINT32 lane13 : 2;
    /* lane13 - Bits[27:26], RWS_L, default = 2'b11  */
    UINT32 lane14 : 2;
    /* lane14 - Bits[29:28], RWS_L, default = 2'b11  */
    UINT32 lane15 : 2;
    /* lane15 - Bits[31:30], RWS_L, default = 2'b11  */
  } Bits;
  UINT32 Data;
} TX_RTERM_PULLHIGH_N_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_RTERM_PULLHIGH_P_IIO_DFX_REG supported on:                              */
/*       IVT_EP (0x400337DC)                                                  */
/*       IVT_EX (0x400337DC)                                                  */
/*       HSX (0x400337DC)                                                     */
/*       BDX (0x400337DC)                                                     */
/* Register default value:              0xFFFFFFFF                            */
#define TX_RTERM_PULLHIGH_P_IIO_DFX_REG 0x120047DC
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x7dc
 */
typedef union {
  struct {
    UINT32 lane0 : 2;
    /* lane0 - Bits[1:0], RWS_L, default = 2'b11  */
    UINT32 lane1 : 2;
    /* lane1 - Bits[3:2], RWS_L, default = 2'b11  */
    UINT32 lane2 : 2;
    /* lane2 - Bits[5:4], RWS_L, default = 2'b11  */
    UINT32 lane3 : 2;
    /* lane3 - Bits[7:6], RWS_L, default = 2'b11  */
    UINT32 lane4 : 2;
    /* lane4 - Bits[9:8], RWS_L, default = 2'b11  */
    UINT32 lane5 : 2;
    /* lane5 - Bits[11:10], RWS_L, default = 2'b11  */
    UINT32 lane6 : 2;
    /* lane6 - Bits[13:12], RWS_L, default = 2'b11  */
    UINT32 lane7 : 2;
    /* lane7 - Bits[15:14], RWS_L, default = 2'b11  */
    UINT32 lane8 : 2;
    /* lane8 - Bits[17:16], RWS_L, default = 2'b11  */
    UINT32 lane9 : 2;
    /* lane9 - Bits[19:18], RWS_L, default = 2'b11  */
    UINT32 lane10 : 2;
    /* lane10 - Bits[21:20], RWS_L, default = 2'b11  */
    UINT32 lane11 : 2;
    /* lane11 - Bits[23:22], RWS_L, default = 2'b11  */
    UINT32 lane12 : 2;
    /* lane12 - Bits[25:24], RWS_L, default = 2'b11  */
    UINT32 lane13 : 2;
    /* lane13 - Bits[27:26], RWS_L, default = 2'b11  */
    UINT32 lane14 : 2;
    /* lane14 - Bits[29:28], RWS_L, default = 2'b11  */
    UINT32 lane15 : 2;
    /* lane15 - Bits[31:30], RWS_L, default = 2'b11  */
  } Bits;
  UINT32 Data;
} TX_RTERM_PULLHIGH_P_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_RX_DET_IIO_DFX_REG supported on:                                        */
/*       IVT_EP (0x40033804)                                                  */
/*       IVT_EX (0x40033804)                                                  */
/*       HSX (0x40033804)                                                     */
/*       BDX (0x40033804)                                                     */
/* Register default value:              0x0000FFFF                            */
#define TX_RX_DET_IIO_DFX_REG 0x12004804
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x804
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RO_V, default = 1'b1  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RO_V, default = 1'b1  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RO_V, default = 1'b1  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RO_V, default = 1'b1  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RO_V, default = 1'b1  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RO_V, default = 1'b1  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RO_V, default = 1'b1  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RO_V, default = 1'b1  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RO_V, default = 1'b1  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RO_V, default = 1'b1  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RO_V, default = 1'b1  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RO_V, default = 1'b1  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RO_V, default = 1'b1  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RO_V, default = 1'b1  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RO_V, default = 1'b1  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RO_V, default = 1'b1  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_RX_DET_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_SPARE_0_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x40033808)                                                  */
/*       IVT_EX (0x40033808)                                                  */
/*       HSX (0x40033808)                                                     */
/*       BDX (0x40033808)                                                     */
/* Register default value:              0xAAAAAAAA                            */
#define TX_SPARE_0_IIO_DFX_REG 0x12004808
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x808
 */
typedef union {
  struct {
    UINT32 lane0 : 4;
    /* lane0 - Bits[3:0], RWS_L, default = 4'b1010  */
    UINT32 lane1 : 4;
    /* lane1 - Bits[7:4], RWS_L, default = 4'b1010  */
    UINT32 lane2 : 4;
    /* lane2 - Bits[11:8], RWS_L, default = 4'b1010  */
    UINT32 lane3 : 4;
    /* lane3 - Bits[15:12], RWS_L, default = 4'b1010  */
    UINT32 lane4 : 4;
    /* lane4 - Bits[19:16], RWS_L, default = 4'b1010  */
    UINT32 lane5 : 4;
    /* lane5 - Bits[23:20], RWS_L, default = 4'b1010  */
    UINT32 lane6 : 4;
    /* lane6 - Bits[27:24], RWS_L, default = 4'b1010  */
    UINT32 lane7 : 4;
    /* lane7 - Bits[31:28], RWS_L, default = 4'b1010  */
  } Bits;
  UINT32 Data;
} TX_SPARE_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_SPARE_1_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x4003380C)                                                  */
/*       IVT_EX (0x4003380C)                                                  */
/*       HSX (0x4003380C)                                                     */
/*       BDX (0x4003380C)                                                     */
/* Register default value:              0xAAAAAAAA                            */
#define TX_SPARE_1_IIO_DFX_REG 0x1200480C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x80c
 */
typedef union {
  struct {
    UINT32 lane8 : 4;
    /* lane8 - Bits[3:0], RWS_L, default = 4'b1010  */
    UINT32 lane9 : 4;
    /* lane9 - Bits[7:4], RWS_L, default = 4'b1010  */
    UINT32 lane10 : 4;
    /* lane10 - Bits[11:8], RWS_L, default = 4'b1010  */
    UINT32 lane11 : 4;
    /* lane11 - Bits[15:12], RWS_L, default = 4'b1010  */
    UINT32 lane12 : 4;
    /* lane12 - Bits[19:16], RWS_L, default = 4'b1010  */
    UINT32 lane13 : 4;
    /* lane13 - Bits[23:20], RWS_L, default = 4'b1010  */
    UINT32 lane14 : 4;
    /* lane14 - Bits[27:24], RWS_L, default = 4'b1010  */
    UINT32 lane15 : 4;
    /* lane15 - Bits[31:28], RWS_L, default = 4'b1010  */
  } Bits;
  UINT32 Data;
} TX_SPARE_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_LCL_ICOMP_DIS_IIO_DFX_REG supported on:                                 */
/*       IVT_EP (0x40033818)                                                  */
/*       IVT_EX (0x40033818)                                                  */
/*       HSX (0x40033818)                                                     */
/*       BDX (0x40033818)                                                     */
/* Register default value:              0x00000000                            */
#define TX_LCL_ICOMP_DIS_IIO_DFX_REG 0x12004818
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x818
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_LCL_ICOMP_DIS_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_DRVSW_CTL_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x4003381C)                                                  */
/*       IVT_EX (0x4003381C)                                                  */
/*       HSX (0x4003381C)                                                     */
/*       BDX (0x4003381C)                                                     */
/* Register default value:              0x00000000                            */
#define TX_DRVSW_CTL_IIO_DFX_REG 0x1200481C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x81c
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_DRVSW_CTL_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_DRVSW_ON_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x40033820)                                                  */
/*       IVT_EX (0x40033820)                                                  */
/*       HSX (0x40033820)                                                     */
/*       BDX (0x40033820)                                                     */
/* Register default value:              0x55555555                            */
#define TX_DRVSW_ON_IIO_DFX_REG 0x12004820
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x820
 */
typedef union {
  struct {
    UINT32 lane0 : 2;
    /* lane0 - Bits[1:0], RWS_L, default = 2'b01  */
    UINT32 lane1 : 2;
    /* lane1 - Bits[3:2], RWS_L, default = 2'b01  */
    UINT32 lane2 : 2;
    /* lane2 - Bits[5:4], RWS_L, default = 2'b01  */
    UINT32 lane3 : 2;
    /* lane3 - Bits[7:6], RWS_L, default = 2'b01  */
    UINT32 lane4 : 2;
    /* lane4 - Bits[9:8], RWS_L, default = 2'b01  */
    UINT32 lane5 : 2;
    /* lane5 - Bits[11:10], RWS_L, default = 2'b01  */
    UINT32 lane6 : 2;
    /* lane6 - Bits[13:12], RWS_L, default = 2'b01  */
    UINT32 lane7 : 2;
    /* lane7 - Bits[15:14], RWS_L, default = 2'b01  */
    UINT32 lane8 : 2;
    /* lane8 - Bits[17:16], RWS_L, default = 2'b01  */
    UINT32 lane9 : 2;
    /* lane9 - Bits[19:18], RWS_L, default = 2'b01  */
    UINT32 lane10 : 2;
    /* lane10 - Bits[21:20], RWS_L, default = 2'b01  */
    UINT32 lane11 : 2;
    /* lane11 - Bits[23:22], RWS_L, default = 2'b01  */
    UINT32 lane12 : 2;
    /* lane12 - Bits[25:24], RWS_L, default = 2'b01  */
    UINT32 lane13 : 2;
    /* lane13 - Bits[27:26], RWS_L, default = 2'b01  */
    UINT32 lane14 : 2;
    /* lane14 - Bits[29:28], RWS_L, default = 2'b01  */
    UINT32 lane15 : 2;
    /* lane15 - Bits[31:30], RWS_L, default = 2'b01  */
  } Bits;
  UINT32 Data;
} TX_DRVSW_ON_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_DTSW_CTL_0_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x40033828)                                                  */
/*       IVT_EX (0x40033828)                                                  */
/*       HSX (0x40033828)                                                     */
/*       BDX (0x40033828)                                                     */
/* Register default value:              0x44444444                            */
#define TX_DTSW_CTL_0_IIO_DFX_REG 0x12004828
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x828
 */
typedef union {
  struct {
    UINT32 lane0 : 4;
    /* lane0 - Bits[3:0], RWS_L, default = 4'b0100  */
    UINT32 lane1 : 4;
    /* lane1 - Bits[7:4], RWS_L, default = 4'b0100  */
    UINT32 lane2 : 4;
    /* lane2 - Bits[11:8], RWS_L, default = 4'b0100  */
    UINT32 lane3 : 4;
    /* lane3 - Bits[15:12], RWS_L, default = 4'b0100  */
    UINT32 lane4 : 4;
    /* lane4 - Bits[19:16], RWS_L, default = 4'b0100  */
    UINT32 lane5 : 4;
    /* lane5 - Bits[23:20], RWS_L, default = 4'b0100  */
    UINT32 lane6 : 4;
    /* lane6 - Bits[27:24], RWS_L, default = 4'b0100  */
    UINT32 lane7 : 4;
    /* lane7 - Bits[31:28], RWS_L, default = 4'b0100  */
  } Bits;
  UINT32 Data;
} TX_DTSW_CTL_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_DTSW_CTL_1_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x4003382C)                                                  */
/*       IVT_EX (0x4003382C)                                                  */
/*       HSX (0x4003382C)                                                     */
/*       BDX (0x4003382C)                                                     */
/* Register default value:              0x44444444                            */
#define TX_DTSW_CTL_1_IIO_DFX_REG 0x1200482C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x82c
 */
typedef union {
  struct {
    UINT32 lane8 : 4;
    /* lane8 - Bits[3:0], RWS_L, default = 4'b0100  */
    UINT32 lane9 : 4;
    /* lane9 - Bits[7:4], RWS_L, default = 4'b0100  */
    UINT32 lane10 : 4;
    /* lane10 - Bits[11:8], RWS_L, default = 4'b0100  */
    UINT32 lane11 : 4;
    /* lane11 - Bits[15:12], RWS_L, default = 4'b0100  */
    UINT32 lane12 : 4;
    /* lane12 - Bits[19:16], RWS_L, default = 4'b0100  */
    UINT32 lane13 : 4;
    /* lane13 - Bits[23:20], RWS_L, default = 4'b0100  */
    UINT32 lane14 : 4;
    /* lane14 - Bits[27:24], RWS_L, default = 4'b0100  */
    UINT32 lane15 : 4;
    /* lane15 - Bits[31:28], RWS_L, default = 4'b0100  */
  } Bits;
  UINT32 Data;
} TX_DTSW_CTL_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_IREF_CTL_0_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x40033838)                                                  */
/*       IVT_EX (0x40033838)                                                  */
/*       HSX (0x40033838)                                                     */
/*       BDX (0x40033838)                                                     */
/* Register default value:              0x00000000                            */
#define TX_IREF_CTL_0_IIO_DFX_REG 0x12004838
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x838
 */
typedef union {
  struct {
    UINT32 bndl0 : 5;
    /* bndl0 - Bits[4:0], RWS_L, default = 5'b00000  */
    UINT32 bndl1 : 5;
    /* bndl1 - Bits[9:5], RWS_L, default = 5'b00000  */
    UINT32 bndl2 : 5;
    /* bndl2 - Bits[14:10], RWS_L, default = 5'b00000  */
    UINT32 bndl3 : 5;
    /* bndl3 - Bits[19:15], RWS_L, default = 5'b00000  */
    UINT32 bndl4 : 5;
    /* bndl4 - Bits[24:20], RWS_L, default = 5'b00000  */
    UINT32 bndl5 : 5;
    /* bndl5 - Bits[29:25], RWS_L, default = 5'b00000  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_IREF_CTL_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_IREF_CTL_1_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x4003383C)                                                  */
/*       IVT_EX (0x4003383C)                                                  */
/*       HSX (0x4003383C)                                                     */
/*       BDX (0x4003383C)                                                     */
/* Register default value:              0x00000000                            */
#define TX_IREF_CTL_1_IIO_DFX_REG 0x1200483C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x83c
 */
typedef union {
  struct {
    UINT32 bndl6 : 5;
    /* bndl6 - Bits[4:0], RWS_L, default = 5'b00000  */
    UINT32 bndl7 : 5;
    /* bndl7 - Bits[9:5], RWS_L, default = 5'b00000  */
    UINT32 rsvd : 22;
    /* rsvd - Bits[31:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_IREF_CTL_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_VREF_SEL_0_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x40033840)                                                  */
/*       IVT_EX (0x40033840)                                                  */
/*       HSX (0x40033840)                                                     */
/*       BDX (0x40033840)                                                     */
/* Register default value:              0x16B5AD6B                            */
#define TX_VREF_SEL_0_IIO_DFX_REG 0x12004840
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x840
 */
typedef union {
  struct {
    UINT32 bndl0 : 5;
    /* bndl0 - Bits[4:0], RWS_L, default = 5'b01011  */
    UINT32 bndl1 : 5;
    /* bndl1 - Bits[9:5], RWS_L, default = 5'b01011  */
    UINT32 bndl2 : 5;
    /* bndl2 - Bits[14:10], RWS_L, default = 5'b01011  */
    UINT32 bndl3 : 5;
    /* bndl3 - Bits[19:15], RWS_L, default = 5'b01011  */
    UINT32 bndl4 : 5;
    /* bndl4 - Bits[24:20], RWS_L, default = 5'b01011  */
    UINT32 bndl5 : 5;
    /* bndl5 - Bits[29:25], RWS_L, default = 5'b01011  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_VREF_SEL_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_VREF_SEL_1_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x40033844)                                                  */
/*       IVT_EX (0x40033844)                                                  */
/*       HSX (0x40033844)                                                     */
/*       BDX (0x40033844)                                                     */
/* Register default value:              0x0000016B                            */
#define TX_VREF_SEL_1_IIO_DFX_REG 0x12004844
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x844
 */
typedef union {
  struct {
    UINT32 bndl6 : 5;
    /* bndl6 - Bits[4:0], RWS_L, default = 5'b01011  */
    UINT32 bndl7 : 5;
    /* bndl7 - Bits[9:5], RWS_L, default = 5'b01011  */
    UINT32 rsvd : 22;
    /* rsvd - Bits[31:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_VREF_SEL_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_RXLPCLK_SEL_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x40033848)                                                  */
/*       IVT_EX (0x40033848)                                                  */
/*       HSX (0x40033848)                                                     */
/*       BDX (0x40033848)                                                     */
/* Register default value:              0x00000000                            */
#define TX_RXLPCLK_SEL_IIO_DFX_REG 0x12004848
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x848
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_RXLPCLK_SEL_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_SENSE_LANE_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x4003384C)                                                  */
/*       IVT_EX (0x4003384C)                                                  */
/*       HSX (0x4003384C)                                                     */
/*       BDX (0x4003384C)                                                     */
/* Register default value:              0x00000000                            */
#define TX_SENSE_LANE_IIO_DFX_REG 0x1200484C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x84c
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_SENSE_LANE_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* OC_START_IIO_DFX_REG supported on:                                         */
/*       IVT_EP (0x40033868)                                                  */
/*       IVT_EX (0x40033868)                                                  */
/*       HSX (0x40033868)                                                     */
/*       BDX (0x40033868)                                                     */
/* Register default value:              0x00000000                            */
#define OC_START_IIO_DFX_REG 0x12004868
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x868
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 15;
    /* rsvd - Bits[30:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 override_enable : 1;
    /* override_enable - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} OC_START_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* OC_DONE_IIO_DFX_REG supported on:                                          */
/*       IVT_EP (0x4003386C)                                                  */
/*       IVT_EX (0x4003386C)                                                  */
/*       HSX (0x4003386C)                                                     */
/*       BDX (0x4003386C)                                                     */
/* Register default value:              0x00000000                            */
#define OC_DONE_IIO_DFX_REG 0x1200486C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x86c
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RO_V, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RO_V, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RO_V, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RO_V, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RO_V, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RO_V, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RO_V, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RO_V, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RO_V, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RO_V, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RO_V, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RO_V, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RO_V, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RO_V, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RO_V, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RO_V, default = 1'b0  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} OC_DONE_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* L0S_RX_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x40033870)                                                  */
/*       IVT_EX (0x40033870)                                                  */
/*       HSX (0x40033870)                                                     */
/*       BDX (0x40033870)                                                     */
/* Register default value:              0x00000000                            */
#define L0S_RX_IIO_DFX_REG 0x12004870
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x870
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 15;
    /* rsvd - Bits[30:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 override_enable : 1;
    /* override_enable - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} L0S_RX_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* L0S_TX_IIO_DFX_REG supported on:                                           */
/*       IVT_EP (0x40033874)                                                  */
/*       IVT_EX (0x40033874)                                                  */
/*       HSX (0x40033874)                                                     */
/*       BDX (0x40033874)                                                     */
/* Register default value:              0x00000000                            */
#define L0S_TX_IIO_DFX_REG 0x12004874
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x874
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 15;
    /* rsvd - Bits[30:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 override_enable : 1;
    /* override_enable - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} L0S_TX_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* L1_MODE_IIO_DFX_REG supported on:                                          */
/*       IVT_EP (0x40033878)                                                  */
/*       IVT_EX (0x40033878)                                                  */
/*       HSX (0x40033878)                                                     */
/*       BDX (0x40033878)                                                     */
/* Register default value:              0x00000000                            */
#define L1_MODE_IIO_DFX_REG 0x12004878
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x878
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 15;
    /* rsvd - Bits[30:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 override_enable : 1;
    /* override_enable - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} L1_MODE_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_LANE_CAL_RST_IIO_DFX_REG supported on:                                  */
/*       IVT_EP (0x4003387C)                                                  */
/*       IVT_EX (0x4003387C)                                                  */
/*       HSX (0x4003387C)                                                     */
/*       BDX (0x4003387C)                                                     */
/* Register default value:              0x00000000                            */
#define RX_LANE_CAL_RST_IIO_DFX_REG 0x1200487C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x87c
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 15;
    /* rsvd - Bits[30:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 override_enable : 1;
    /* override_enable - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} RX_LANE_CAL_RST_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_RESET_IIO_DFX_REG supported on:                                         */
/*       IVT_EP (0x40033880)                                                  */
/*       IVT_EX (0x40033880)                                                  */
/*       HSX (0x40033880)                                                     */
/*       BDX (0x40033880)                                                     */
/* Register default value:              0x00000000                            */
#define RX_RESET_IIO_DFX_REG 0x12004880
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x880
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 15;
    /* rsvd - Bits[30:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 override_enable : 1;
    /* override_enable - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} RX_RESET_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_RESET_IIO_DFX_REG supported on:                                         */
/*       IVT_EP (0x40033884)                                                  */
/*       IVT_EX (0x40033884)                                                  */
/*       HSX (0x40033884)                                                     */
/*       BDX (0x40033884)                                                     */
/* Register default value:              0x00000000                            */
#define TX_RESET_IIO_DFX_REG 0x12004884
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x884
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 rsvd : 15;
    /* rsvd - Bits[30:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 override_enable : 1;
    /* override_enable - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} TX_RESET_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* BNDL_RST_IIO_DFX_REG supported on:                                         */
/*       IVT_EP (0x40033888)                                                  */
/*       IVT_EX (0x40033888)                                                  */
/*       HSX (0x40033888)                                                     */
/*       BDX (0x40033888)                                                     */
/* Register default value:              0x00000000                            */
#define BNDL_RST_IIO_DFX_REG 0x12004888
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x888
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 rsvd : 23;
    /* rsvd - Bits[30:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 override_enable : 1;
    /* override_enable - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} BNDL_RST_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* DFX_BDL_SEL_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x4003388C)                                                  */
/*       IVT_EX (0x4003388C)                                                  */
/*       HSX (0x4003388C)                                                     */
/*       BDX (0x4003388C)                                                     */
/* Register default value:              0x00000000                            */
#define DFX_BDL_SEL_IIO_DFX_REG 0x1200488C
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x88c
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DFX_BDL_SEL_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* EYEMON_TRIG_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x40033894)                                                  */
/*       IVT_EX (0x40033894)                                                  */
/*       HSX (0x40033894)                                                     */
/*       BDX (0x40033894)                                                     */
/* Register default value:              0x00000000                            */
#define EYEMON_TRIG_IIO_DFX_REG 0x12004894
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x894
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_LV, default = 1'b0  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_LV, default = 1'b0  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_LV, default = 1'b0  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_LV, default = 1'b0  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_LV, default = 1'b0  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_LV, default = 1'b0  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_LV, default = 1'b0  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_LV, default = 1'b0  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} EYEMON_TRIG_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TAGSUSEDCNT_IIO_DFX_REG supported on:                                      */
/*       IVT_EP (0x40033898)                                                  */
/*       IVT_EX (0x40033898)                                                  */
/*       HSX (0x40033898)                                                     */
/*       BDX (0x40033898)                                                     */
/* Register default value:              0x00000000                            */
#define TAGSUSEDCNT_IIO_DFX_REG 0x12004898
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0x898
 */
typedef union {
  struct {
    UINT32 alltagsusedcnt : 32;
    /* alltagsusedcnt - Bits[31:0], RW, default = 32'b00000000000000000000000000000000  */
  } Bits;
  UINT32 Data;
} TAGSUSEDCNT_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* BNDL_SPARE2_0_IIO_DFX_REG supported on:                                    */
/*       HSX (0x40033A00)                                                     */
/*       BDX (0x40033A00)                                                     */
/* Register default value:              0x00000000                            */
#define BNDL_SPARE2_0_IIO_DFX_REG 0x12004A00

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa00
 */
typedef union {
  struct {
    UINT32 bndl0 : 8;
    /* bndl0 - Bits[7:0], RWS_L, default = 8'b00000000  */
    UINT32 bndl1 : 8;
    /* bndl1 - Bits[15:8], RWS_L, default = 8'b00000000  */
    UINT32 bndl2 : 8;
    /* bndl2 - Bits[23:16], RWS_L, default = 8'b00000000  */
    UINT32 bndl3 : 8;
    /* bndl3 - Bits[31:24], RWS_L, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} BNDL_SPARE2_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* BNDL_SPARE2_1_IIO_DFX_REG supported on:                                    */
/*       HSX (0x40033A04)                                                     */
/*       BDX (0x40033A04)                                                     */
/* Register default value:              0x00000000                            */
#define BNDL_SPARE2_1_IIO_DFX_REG 0x12004A04

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa04
 */
typedef union {
  struct {
    UINT32 bndl4 : 8;
    /* bndl4 - Bits[7:0], RWS_L, default = 8'b00000000  */
    UINT32 bndl5 : 8;
    /* bndl5 - Bits[15:8], RWS_L, default = 8'b00000000  */
    UINT32 bndl6 : 8;
    /* bndl6 - Bits[23:16], RWS_L, default = 8'b00000000  */
    UINT32 bndl7 : 8;
    /* bndl7 - Bits[31:24], RWS_L, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} BNDL_SPARE2_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* BNDL_SPARE3_0_IIO_DFX_REG supported on:                                    */
/*       HSX (0x40033A08)                                                     */
/*       BDX (0x40033A08)                                                     */
/* Register default value:              0x00000000                            */
#define BNDL_SPARE3_0_IIO_DFX_REG 0x12004A08

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa08
 */
typedef union {
  struct {
    UINT32 bndl0 : 8;
    /* bndl0 - Bits[7:0], RWS_L, default = 8'b00000000  */
    UINT32 bndl1 : 8;
    /* bndl1 - Bits[15:8], RWS_L, default = 8'b00000000  */
    UINT32 bndl2 : 8;
    /* bndl2 - Bits[23:16], RWS_L, default = 8'b00000000  */
    UINT32 bndl3 : 8;
    /* bndl3 - Bits[31:24], RWS_L, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} BNDL_SPARE3_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* BNDL_SPARE3_1_IIO_DFX_REG supported on:                                    */
/*       HSX (0x40033A0C)                                                     */
/*       BDX (0x40033A0C)                                                     */
/* Register default value:              0x00000000                            */
#define BNDL_SPARE3_1_IIO_DFX_REG 0x12004A0C

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa0c
 */
typedef union {
  struct {
    UINT32 bndl4 : 8;
    /* bndl4 - Bits[7:0], RWS_L, default = 8'b00000000  */
    UINT32 bndl5 : 8;
    /* bndl5 - Bits[15:8], RWS_L, default = 8'b00000000  */
    UINT32 bndl6 : 8;
    /* bndl6 - Bits[23:16], RWS_L, default = 8'b00000000  */
    UINT32 bndl7 : 8;
    /* bndl7 - Bits[31:24], RWS_L, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} BNDL_SPARE3_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* BNDL_SPARE4_0_IIO_DFX_REG supported on:                                    */
/*       HSX (0x40033A10)                                                     */
/*       BDX (0x40033A10)                                                     */
/* Register default value:              0x00000000                            */
#define BNDL_SPARE4_0_IIO_DFX_REG 0x12004A10

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa10
 */
typedef union {
  struct {
    UINT32 bndl0 : 8;
    /* bndl0 - Bits[7:0], RWS_L, default = 8'b00000000  */
    UINT32 bndl1 : 8;
    /* bndl1 - Bits[15:8], RWS_L, default = 8'b00000000  */
    UINT32 bndl2 : 8;
    /* bndl2 - Bits[23:16], RWS_L, default = 8'b00000000  */
    UINT32 bndl3 : 8;
    /* bndl3 - Bits[31:24], RWS_L, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} BNDL_SPARE4_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* BNDL_SPARE4_1_IIO_DFX_REG supported on:                                    */
/*       HSX (0x40033A14)                                                     */
/*       BDX (0x40033A14)                                                     */
/* Register default value:              0x00000000                            */
#define BNDL_SPARE4_1_IIO_DFX_REG 0x12004A14

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa14
 */
typedef union {
  struct {
    UINT32 bndl4 : 8;
    /* bndl4 - Bits[7:0], RWS_L, default = 8'b00000000  */
    UINT32 bndl5 : 8;
    /* bndl5 - Bits[15:8], RWS_L, default = 8'b00000000  */
    UINT32 bndl6 : 8;
    /* bndl6 - Bits[23:16], RWS_L, default = 8'b00000000  */
    UINT32 bndl7 : 8;
    /* bndl7 - Bits[31:24], RWS_L, default = 8'b00000000  */
  } Bits;
  UINT32 Data;
} BNDL_SPARE4_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* TX_ADAPT_DELTA_SW_L0_IIO_DFX_REG supported on:                             */
/*       IVT_EP (0x40033A24)                                                  */
/*       IVT_EX (0x40033A24)                                                  */
/*       HSX (0x40033A30)                                                     */
/*       BDX (0x40033A30)                                                     */
/* Register default value:              0x00000000                            */
#define TX_ADAPT_DELTA_SW_L0_IIO_DFX_REG 0x1200C000
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa30
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_ADAPT_DELTA_SW_L0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* TX_ADAPT_DELTA_SW_L1_IIO_DFX_REG supported on:                             */
/*       IVT_EP (0x40033A28)                                                  */
/*       IVT_EX (0x40033A28)                                                  */
/*       HSX (0x40033A34)                                                     */
/*       BDX (0x40033A34)                                                     */
/* Register default value:              0x00000000                            */
#define TX_ADAPT_DELTA_SW_L1_IIO_DFX_REG 0x1200C001
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa34
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} TX_ADAPT_DELTA_SW_L1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* BNDL_SPARE_0_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x40033A2C)                                                  */
/*       IVT_EX (0x40033A2C)                                                  */
/*       HSX (0x40033A38)                                                     */
/*       BDX (0x40033A38)                                                     */
/* Register default value on IVT_EP:    0x00180018                            */
/* Register default value on IVT_EX:    0x00180018                            */
/* Register default value on HSX:       0x00180018                            */
/* Register default value on BDX:       0x00380038                            */
#define BNDL_SPARE_0_IIO_DFX_REG 0x1200C002
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa38
 */
typedef union {
  struct {
    UINT32 bndl0 : 16;
    /* bndl0 - Bits[15:0], RWS_L, default = 16'b0000000000111000  */
    UINT32 bndl1 : 16;
    /* bndl1 - Bits[31:16], RWS_L, default = 16'b0000000000111000  */
  } Bits;
  UINT32 Data;
} BNDL_SPARE_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* BNDL_SPARE_1_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x40033A30)                                                  */
/*       IVT_EX (0x40033A30)                                                  */
/*       HSX (0x40033A3C)                                                     */
/*       BDX (0x40033A3C)                                                     */
/* Register default value on IVT_EP:    0x00180018                            */
/* Register default value on IVT_EX:    0x00180018                            */
/* Register default value on HSX:       0x00180018                            */
/* Register default value on BDX:       0x00380038                            */
#define BNDL_SPARE_1_IIO_DFX_REG 0x1200C003
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa3c
 */
typedef union {
  struct {
    UINT32 bndl2 : 16;
    /* bndl2 - Bits[15:0], RWS_L, default = 16'b0000000000111000  */
    UINT32 bndl3 : 16;
    /* bndl3 - Bits[31:16], RWS_L, default = 16'b0000000000111000  */
  } Bits;
  UINT32 Data;
} BNDL_SPARE_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* BNDL_SPARE_2_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x40033A34)                                                  */
/*       IVT_EX (0x40033A34)                                                  */
/*       HSX (0x40033A40)                                                     */
/*       BDX (0x40033A40)                                                     */
/* Register default value on IVT_EP:    0x00180018                            */
/* Register default value on IVT_EX:    0x00180018                            */
/* Register default value on HSX:       0x00180018                            */
/* Register default value on BDX:       0x00380038                            */
#define BNDL_SPARE_2_IIO_DFX_REG 0x1200C004
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa40
 */
typedef union {
  struct {
    UINT32 bndl4 : 16;
    /* bndl4 - Bits[15:0], RWS_L, default = 16'b0000000000111000  */
    UINT32 bndl5 : 16;
    /* bndl5 - Bits[31:16], RWS_L, default = 16'b0000000000111000  */
  } Bits;
  UINT32 Data;
} BNDL_SPARE_2_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* BNDL_SPARE_3_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x40033A38)                                                  */
/*       IVT_EX (0x40033A38)                                                  */
/*       HSX (0x40033A44)                                                     */
/*       BDX (0x40033A44)                                                     */
/* Register default value on IVT_EP:    0x00180018                            */
/* Register default value on IVT_EX:    0x00180018                            */
/* Register default value on HSX:       0x00180018                            */
/* Register default value on BDX:       0x00380038                            */
#define BNDL_SPARE_3_IIO_DFX_REG 0x1200C005
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa44
 */
typedef union {
  struct {
    UINT32 bndl6 : 16;
    /* bndl6 - Bits[15:0], RWS_L, default = 16'b0000000000111000  */
    UINT32 bndl7 : 16;
    /* bndl7 - Bits[31:16], RWS_L, default = 16'b0000000000111000  */
  } Bits;
  UINT32 Data;
} BNDL_SPARE_3_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* ENBL_CDR_HANG_DET_L0_IIO_DFX_REG supported on:                             */
/*       IVT_EP (0x40033A44)                                                  */
/*       IVT_EX (0x40033A44)                                                  */
/*       HSX (0x40033A50)                                                     */
/*       BDX (0x40033A50)                                                     */
/* Register default value:              0x000000FF                            */
#define ENBL_CDR_HANG_DET_L0_IIO_DFX_REG 0x1200C006
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa50
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b1  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b1  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b1  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} ENBL_CDR_HANG_DET_L0_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* ENBL_CDR_HANG_DET_L1_IIO_DFX_REG supported on:                             */
/*       IVT_EP (0x40033A48)                                                  */
/*       IVT_EX (0x40033A48)                                                  */
/*       HSX (0x40033A54)                                                     */
/*       BDX (0x40033A54)                                                     */
/* Register default value:              0x000000FF                            */
#define ENBL_CDR_HANG_DET_L1_IIO_DFX_REG 0x1200C007
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa54
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b1  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b1  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b1  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} ENBL_CDR_HANG_DET_L1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* FFE_BKCH_THRESHOLD_IIO_DFX_REG supported on:                               */
/*       IVT_EP (0x40033A4C)                                                  */
/*       IVT_EX (0x40033A4C)                                                  */
/*       HSX (0x40033A58)                                                     */
/*       BDX (0x40033A58)                                                     */
/* Register default value:              0x00005555                            */
#define FFE_BKCH_THRESHOLD_IIO_DFX_REG 0x1200C008
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa58
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b01  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b01  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b01  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b01  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b01  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b01  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b01  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b01  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} FFE_BKCH_THRESHOLD_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PSA_CFG_GEN2_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x40033A60)                                                  */
/*       IVT_EX (0x40033A60)                                                  */
/*       HSX (0x40033A60)                                                     */
/*       BDX (0x40033A60)                                                     */
/* Register default value on IVT_EP:    0x00005555                            */
/* Register default value on IVT_EX:    0x00005555                            */
/* Register default value on HSX:       0x00005555                            */
/* Register default value on BDX:       0x00000000                            */
#define PSA_CFG_GEN2_IIO_DFX_REG 0x12004A60
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa60
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b00  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b00  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b00  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b00  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b00  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b00  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b00  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b00  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PSA_CFG_GEN2_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* PSA_CFG_GEN3_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x40033A64)                                                  */
/*       IVT_EX (0x40033A64)                                                  */
/*       HSX (0x40033A64)                                                     */
/*       BDX (0x40033A64)                                                     */
/* Register default value:              0x00005555                            */
#define PSA_CFG_GEN3_IIO_DFX_REG 0x12004A64
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa64
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b01  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b01  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b01  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b01  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b01  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b01  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b01  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b01  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} PSA_CFG_GEN3_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* RX_VCM_SUM_SEL_EXTND_IIO_DFX_REG supported on:                             */
/*       BDX (0x40033A68)                                                     */
/* Register default value:              0x00000000                            */
#define RX_VCM_SUM_SEL_EXTND_IIO_DFX_REG 0x12004A68

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa68
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_VCM_SUM_SEL_EXTND_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* L0ACTIVE_IIO_DFX_REG supported on:                                         */
/*       BDX (0x40033A6C)                                                     */
/* Register default value:              0x0000FFFF                            */
#define L0ACTIVE_IIO_DFX_REG 0x12004A6C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa6c
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b1  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b1  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b1  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b1  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b1  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b1  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b1  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b1  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b1  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b1  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b1  */
    UINT32 rsvd : 15;
    /* rsvd - Bits[30:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 override_enable : 1;
    /* override_enable - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} L0ACTIVE_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* RX_CTLE_PEAK_GEN1_0_IIO_DFX_REG supported on:                              */
/*       HSX (0x40033A70)                                                     */
/*       BDX (0x40033A70)                                                     */
/* Register default value:              0x02108421                            */
#define RX_CTLE_PEAK_GEN1_0_IIO_DFX_REG 0x12004A70

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa70
 */
typedef union {
  struct {
    UINT32 bndl0 : 5;
    /* bndl0 - Bits[4:0], RWS_L, default = 5'b00001  */
    UINT32 bndl1 : 5;
    /* bndl1 - Bits[9:5], RWS_L, default = 5'b00001  */
    UINT32 bndl2 : 5;
    /* bndl2 - Bits[14:10], RWS_L, default = 5'b00001  */
    UINT32 bndl3 : 5;
    /* bndl3 - Bits[19:15], RWS_L, default = 5'b00001  */
    UINT32 bndl4 : 5;
    /* bndl4 - Bits[24:20], RWS_L, default = 5'b00001  */
    UINT32 bndl5 : 5;
    /* bndl5 - Bits[29:25], RWS_L, default = 5'b00001  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_CTLE_PEAK_GEN1_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* RX_CTLE_PEAK_GEN1_1_IIO_DFX_REG supported on:                              */
/*       HSX (0x40033A74)                                                     */
/*       BDX (0x40033A74)                                                     */
/* Register default value:              0x00000021                            */
#define RX_CTLE_PEAK_GEN1_1_IIO_DFX_REG 0x12004A74

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa74
 */
typedef union {
  struct {
    UINT32 bndl6 : 5;
    /* bndl6 - Bits[4:0], RWS_L, default = 5'b00001  */
    UINT32 bndl7 : 5;
    /* bndl7 - Bits[9:5], RWS_L, default = 5'b00001  */
    UINT32 rsvd : 22;
    /* rsvd - Bits[31:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_CTLE_PEAK_GEN1_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* RX_CTLE_PEAK_GEN2_0_IIO_DFX_REG supported on:                              */
/*       HSX (0x40033A78)                                                     */
/*       BDX (0x40033A78)                                                     */
/* Register default value:              0x0E739CE7                            */
#define RX_CTLE_PEAK_GEN2_0_IIO_DFX_REG 0x12004A78

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa78
 */
typedef union {
  struct {
    UINT32 bndl0 : 5;
    /* bndl0 - Bits[4:0], RWS_L, default = 5'b00111  */
    UINT32 bndl1 : 5;
    /* bndl1 - Bits[9:5], RWS_L, default = 5'b00111  */
    UINT32 bndl2 : 5;
    /* bndl2 - Bits[14:10], RWS_L, default = 5'b00111  */
    UINT32 bndl3 : 5;
    /* bndl3 - Bits[19:15], RWS_L, default = 5'b00111  */
    UINT32 bndl4 : 5;
    /* bndl4 - Bits[24:20], RWS_L, default = 5'b00111  */
    UINT32 bndl5 : 5;
    /* bndl5 - Bits[29:25], RWS_L, default = 5'b00111  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_CTLE_PEAK_GEN2_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* RX_CTLE_PEAK_GEN2_1_IIO_DFX_REG supported on:                              */
/*       HSX (0x40033A7C)                                                     */
/*       BDX (0x40033A7C)                                                     */
/* Register default value:              0x000000E7                            */
#define RX_CTLE_PEAK_GEN2_1_IIO_DFX_REG 0x12004A7C

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa7c
 */
typedef union {
  struct {
    UINT32 bndl6 : 5;
    /* bndl6 - Bits[4:0], RWS_L, default = 5'b00111  */
    UINT32 bndl7 : 5;
    /* bndl7 - Bits[9:5], RWS_L, default = 5'b00111  */
    UINT32 rsvd : 22;
    /* rsvd - Bits[31:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_CTLE_PEAK_GEN2_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* RX_CTLE_PEAK_GEN3_0_IIO_DFX_REG supported on:                              */
/*       HSX (0x40033A80)                                                     */
/*       BDX (0x40033A80)                                                     */
/* Register default value:              0x0E739CE7                            */
#define RX_CTLE_PEAK_GEN3_0_IIO_DFX_REG 0x12004A80

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa80
 */
typedef union {
  struct {
    UINT32 bndl0 : 5;
    /* bndl0 - Bits[4:0], RWS_L, default = 5'b00111  */
    UINT32 bndl1 : 5;
    /* bndl1 - Bits[9:5], RWS_L, default = 5'b00111  */
    UINT32 bndl2 : 5;
    /* bndl2 - Bits[14:10], RWS_L, default = 5'b00111  */
    UINT32 bndl3 : 5;
    /* bndl3 - Bits[19:15], RWS_L, default = 5'b00111  */
    UINT32 bndl4 : 5;
    /* bndl4 - Bits[24:20], RWS_L, default = 5'b00111  */
    UINT32 bndl5 : 5;
    /* bndl5 - Bits[29:25], RWS_L, default = 5'b00111  */
    UINT32 rsvd : 2;
    /* rsvd - Bits[31:30], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_CTLE_PEAK_GEN3_0_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* RX_CTLE_PEAK_GEN3_1_IIO_DFX_REG supported on:                              */
/*       HSX (0x40033A84)                                                     */
/*       BDX (0x40033A84)                                                     */
/* Register default value:              0x000000E7                            */
#define RX_CTLE_PEAK_GEN3_1_IIO_DFX_REG 0x12004A84

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa84
 */
typedef union {
  struct {
    UINT32 bndl6 : 5;
    /* bndl6 - Bits[4:0], RWS_L, default = 5'b00111  */
    UINT32 bndl7 : 5;
    /* bndl7 - Bits[9:5], RWS_L, default = 5'b00111  */
    UINT32 rsvd : 22;
    /* rsvd - Bits[31:10], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RX_CTLE_PEAK_GEN3_1_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* RX_CTLE_RDEG_GEN1_IIO_DFX_REG supported on:                                */
/*       HSX (0x40033A88)                                                     */
/*       BDX (0x40033A88)                                                     */
/* Register default value:              0x33333333                            */
#define RX_CTLE_RDEG_GEN1_IIO_DFX_REG 0x12004A88

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa88
 */
typedef union {
  struct {
    UINT32 bndl0 : 4;
    /* bndl0 - Bits[3:0], RWS_L, default = 4'b0011  */
    UINT32 bndl1 : 4;
    /* bndl1 - Bits[7:4], RWS_L, default = 4'b0011  */
    UINT32 bndl2 : 4;
    /* bndl2 - Bits[11:8], RWS_L, default = 4'b0011  */
    UINT32 bndl3 : 4;
    /* bndl3 - Bits[15:12], RWS_L, default = 4'b0011  */
    UINT32 bndl4 : 4;
    /* bndl4 - Bits[19:16], RWS_L, default = 4'b0011  */
    UINT32 bndl5 : 4;
    /* bndl5 - Bits[23:20], RWS_L, default = 4'b0011  */
    UINT32 bndl6 : 4;
    /* bndl6 - Bits[27:24], RWS_L, default = 4'b0011  */
    UINT32 bndl7 : 4;
    /* bndl7 - Bits[31:28], RWS_L, default = 4'b0011  */
  } Bits;
  UINT32 Data;
} RX_CTLE_RDEG_GEN1_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* RX_CTLE_RDEG_GEN2_IIO_DFX_REG supported on:                                */
/*       HSX (0x40033A8C)                                                     */
/*       BDX (0x40033A8C)                                                     */
/* Register default value:              0x33333333                            */
#define RX_CTLE_RDEG_GEN2_IIO_DFX_REG 0x12004A8C

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa8c
 */
typedef union {
  struct {
    UINT32 bndl0 : 4;
    /* bndl0 - Bits[3:0], RWS_L, default = 4'b0011  */
    UINT32 bndl1 : 4;
    /* bndl1 - Bits[7:4], RWS_L, default = 4'b0011  */
    UINT32 bndl2 : 4;
    /* bndl2 - Bits[11:8], RWS_L, default = 4'b0011  */
    UINT32 bndl3 : 4;
    /* bndl3 - Bits[15:12], RWS_L, default = 4'b0011  */
    UINT32 bndl4 : 4;
    /* bndl4 - Bits[19:16], RWS_L, default = 4'b0011  */
    UINT32 bndl5 : 4;
    /* bndl5 - Bits[23:20], RWS_L, default = 4'b0011  */
    UINT32 bndl6 : 4;
    /* bndl6 - Bits[27:24], RWS_L, default = 4'b0011  */
    UINT32 bndl7 : 4;
    /* bndl7 - Bits[31:28], RWS_L, default = 4'b0011  */
  } Bits;
  UINT32 Data;
} RX_CTLE_RDEG_GEN2_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* RX_CTLE_RDEG_GEN3_IIO_DFX_REG supported on:                                */
/*       HSX (0x40033A90)                                                     */
/*       BDX (0x40033A90)                                                     */
/* Register default value:              0x33333333                            */
#define RX_CTLE_RDEG_GEN3_IIO_DFX_REG 0x12004A90

#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa90
 */
typedef union {
  struct {
    UINT32 bndl0 : 4;
    /* bndl0 - Bits[3:0], RWS_L, default = 4'b0011  */
    UINT32 bndl1 : 4;
    /* bndl1 - Bits[7:4], RWS_L, default = 4'b0011  */
    UINT32 bndl2 : 4;
    /* bndl2 - Bits[11:8], RWS_L, default = 4'b0011  */
    UINT32 bndl3 : 4;
    /* bndl3 - Bits[15:12], RWS_L, default = 4'b0011  */
    UINT32 bndl4 : 4;
    /* bndl4 - Bits[19:16], RWS_L, default = 4'b0011  */
    UINT32 bndl5 : 4;
    /* bndl5 - Bits[23:20], RWS_L, default = 4'b0011  */
    UINT32 bndl6 : 4;
    /* bndl6 - Bits[27:24], RWS_L, default = 4'b0011  */
    UINT32 bndl7 : 4;
    /* bndl7 - Bits[31:28], RWS_L, default = 4'b0011  */
  } Bits;
  UINT32 Data;
} RX_CTLE_RDEG_GEN3_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /* defined(HSX_HOST) || defined(BDX_HOST) */


/* RXSQLCOMPLIANCE_IIO_DFX_REG supported on:                                  */
/*       BDX (0x40033A94)                                                     */
/* Register default value:              0x0000FFFF                            */
#define RXSQLCOMPLIANCE_IIO_DFX_REG 0x12004A94

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa94
 */
typedef union {
  struct {
    UINT32 lane0 : 1;
    /* lane0 - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 lane1 : 1;
    /* lane1 - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 lane2 : 1;
    /* lane2 - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 lane3 : 1;
    /* lane3 - Bits[3:3], RWS_L, default = 1'b1  */
    UINT32 lane4 : 1;
    /* lane4 - Bits[4:4], RWS_L, default = 1'b1  */
    UINT32 lane5 : 1;
    /* lane5 - Bits[5:5], RWS_L, default = 1'b1  */
    UINT32 lane6 : 1;
    /* lane6 - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 lane7 : 1;
    /* lane7 - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 lane8 : 1;
    /* lane8 - Bits[8:8], RWS_L, default = 1'b1  */
    UINT32 lane9 : 1;
    /* lane9 - Bits[9:9], RWS_L, default = 1'b1  */
    UINT32 lane10 : 1;
    /* lane10 - Bits[10:10], RWS_L, default = 1'b1  */
    UINT32 lane11 : 1;
    /* lane11 - Bits[11:11], RWS_L, default = 1'b1  */
    UINT32 lane12 : 1;
    /* lane12 - Bits[12:12], RWS_L, default = 1'b1  */
    UINT32 lane13 : 1;
    /* lane13 - Bits[13:13], RWS_L, default = 1'b1  */
    UINT32 lane14 : 1;
    /* lane14 - Bits[14:14], RWS_L, default = 1'b1  */
    UINT32 lane15 : 1;
    /* lane15 - Bits[15:15], RWS_L, default = 1'b1  */
    UINT32 rsvd : 15;
    /* rsvd - Bits[30:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 override_enable : 1;
    /* override_enable - Bits[31:31], RWS_L, default = 1'b0  */
  } Bits;
  UINT32 Data;
} RXSQLCOMPLIANCE_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DCBLEED_PD_IIO_DFX_REG supported on:                                       */
/*       BDX (0x40033A98)                                                     */
/* Register default value:              0x000000FF                            */
#define DCBLEED_PD_IIO_DFX_REG 0x12004A98

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa98
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b1  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b1  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b1  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DCBLEED_PD_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* RATESEL_EN_CAP_DIV_IIO_DFX_REG supported on:                               */
/*       BDX (0x40033A9C)                                                     */
/* Register default value:              0x000000FF                            */
#define RATESEL_EN_CAP_DIV_IIO_DFX_REG 0x12004A9C

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xa9c
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b1  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b1  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b1  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RATESEL_EN_CAP_DIV_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* RATESEL_DISABLE_TWG_IIO_DFX_REG supported on:                              */
/*       BDX (0x40033AA0)                                                     */
/* Register default value:              0x00000000                            */
#define RATESEL_DISABLE_TWG_IIO_DFX_REG 0x12004AA0

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xaa0
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RATESEL_DISABLE_TWG_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* MIXER_DEGEN_DIS_IIO_DFX_REG supported on:                                  */
/*       BDX (0x40033AA4)                                                     */
/* Register default value:              0x00000000                            */
#define MIXER_DEGEN_DIS_IIO_DFX_REG 0x12004AA4

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xaa4
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b0  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} MIXER_DEGEN_DIS_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* RLOAD_SLOWCK_IIO_DFX_REG supported on:                                     */
/*       BDX (0x40033AA8)                                                     */
/* Register default value:              0x000000FF                            */
#define RLOAD_SLOWCK_IIO_DFX_REG 0x12004AA8

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xaa8
 */
typedef union {
  struct {
    UINT32 bndl0 : 1;
    /* bndl0 - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 bndl1 : 1;
    /* bndl1 - Bits[1:1], RWS_L, default = 1'b1  */
    UINT32 bndl2 : 1;
    /* bndl2 - Bits[2:2], RWS_L, default = 1'b1  */
    UINT32 bndl3 : 1;
    /* bndl3 - Bits[3:3], RWS_L, default = 1'b1  */
    UINT32 bndl4 : 1;
    /* bndl4 - Bits[4:4], RWS_L, default = 1'b1  */
    UINT32 bndl5 : 1;
    /* bndl5 - Bits[5:5], RWS_L, default = 1'b1  */
    UINT32 bndl6 : 1;
    /* bndl6 - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 bndl7 : 1;
    /* bndl7 - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 rsvd : 24;
    /* rsvd - Bits[31:8], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RLOAD_SLOWCK_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DCBLEED_EN_SINK_IIO_DFX_REG supported on:                                  */
/*       BDX (0x40033AAC)                                                     */
/* Register default value:              0x0000AAAA                            */
#define DCBLEED_EN_SINK_IIO_DFX_REG 0x12004AAC

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xaac
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b10  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b10  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b10  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b10  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b10  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b10  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b10  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b10  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DCBLEED_EN_SINK_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* DCBLEED_EN_SINK_REF_IIO_DFX_REG supported on:                              */
/*       BDX (0x40033AB0)                                                     */
/* Register default value:              0x00005555                            */
#define DCBLEED_EN_SINK_REF_IIO_DFX_REG 0x12004AB0

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xab0
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b01  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b01  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b01  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b01  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b01  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b01  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b01  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b01  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DCBLEED_EN_SINK_REF_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* GAIN_BOOST_IIO_DFX_REG supported on:                                       */
/*       BDX (0x40033AB4)                                                     */
/* Register default value:              0x00005555                            */
#define GAIN_BOOST_IIO_DFX_REG 0x12004AB4

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xab4
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b01  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b01  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b01  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b01  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b01  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b01  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b01  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b01  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} GAIN_BOOST_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */


/* RATESEL_BIAS_TUNE_IIO_DFX_REG supported on:                                */
/*       BDX (0x40033AB8)                                                     */
/* Register default value:              0x00005555                            */
#define RATESEL_BIAS_TUNE_IIO_DFX_REG 0x12004AB8

#ifdef BDX_HOST
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xab8
 */
typedef union {
  struct {
    UINT32 bndl0 : 2;
    /* bndl0 - Bits[1:0], RWS_L, default = 2'b01  */
    UINT32 bndl1 : 2;
    /* bndl1 - Bits[3:2], RWS_L, default = 2'b01  */
    UINT32 bndl2 : 2;
    /* bndl2 - Bits[5:4], RWS_L, default = 2'b01  */
    UINT32 bndl3 : 2;
    /* bndl3 - Bits[7:6], RWS_L, default = 2'b01  */
    UINT32 bndl4 : 2;
    /* bndl4 - Bits[9:8], RWS_L, default = 2'b01  */
    UINT32 bndl5 : 2;
    /* bndl5 - Bits[11:10], RWS_L, default = 2'b01  */
    UINT32 bndl6 : 2;
    /* bndl6 - Bits[13:12], RWS_L, default = 2'b01  */
    UINT32 bndl7 : 2;
    /* bndl7 - Bits[15:14], RWS_L, default = 2'b01  */
    UINT32 rsvd : 16;
    /* rsvd - Bits[31:16], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} RATESEL_BIAS_TUNE_IIO_DFX_STRUCT;
#endif /* ASM_INC */
#endif /*BDX_HOST */




/* DFXCHICKENBIT0_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x40033B04)                                                  */
/*       IVT_EX (0x40033B04)                                                  */
/*       HSX (0x40033B04)                                                     */
/*       BDX (0x40033B04)                                                     */
/* Register default value:              0x00007181                            */
#define DFXCHICKENBIT0_IIO_DFX_REG 0x12004B04
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xb04
 */
typedef union {
  struct {
    UINT32 en_eieos_rec : 1;
    /* en_eieos_rec - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 dis_coeff_extended_eieos : 1;
    /* dis_coeff_extended_eieos - Bits[1:1], RWS_L, default = 1'b0  */
    UINT32 dis_det_l1_mode : 1;
    /* dis_det_l1_mode - Bits[2:2], RWS_L, default = 1'b0  */
    UINT32 dis_rule4a1_check : 1;
    /* dis_rule4a1_check - Bits[3:3], RWS_L, default = 1'b0  */
    UINT32 dis_rule4c1_check : 1;
    /* dis_rule4c1_check - Bits[4:4], RWS_L, default = 1'b0  */
    UINT32 force_indep_pull : 1;
    /* force_indep_pull - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 dis_rule4a2_check : 1;
    /* dis_rule4a2_check - Bits[6:6], RWS_L, default = 1'b0  */
    UINT32 csr_dis_rsteiecount_2cycle : 1;
    /* csr_dis_rsteiecount_2cycle - Bits[7:7], RWS_L, default = 1'b1  */
    UINT32 en_eqts1_in_lpbk_m : 1;
    /* en_eqts1_in_lpbk_m - Bits[8:8], RWS_L, default = 1'b1  */
    UINT32 en_fuse_g2g3 : 1;
    /* en_fuse_g2g3 - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 dis_dferr_chk : 1;
    /* dis_dferr_chk - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 dis_eb_wrptr_hold : 1;
    /* dis_eb_wrptr_hold - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 dis_send_ts1_pol_state : 1;
    /* dis_send_ts1_pol_state - Bits[12:12], RWS_L, default = 1'b1  */
    UINT32 dis_l1exit2w4bitlock1state : 1;
    /* dis_l1exit2w4bitlock1state - Bits[13:13], RWS_L, default = 1'b1  */
    UINT32 dis_cef_cff_x2_x4 : 1;
    /* dis_cef_cff_x2_x4 - Bits[14:14], RWS_L, default = 1'b1  */
    UINT32 dis_l0_rec : 1;
    /* dis_l0_rec - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 cfgrcvto_dis : 1;
    /* cfgrcvto_dis - Bits[16:16], RWS_L, default = 1'b0  */
    UINT32 dis_pollact_sqexit : 1;
    /* dis_pollact_sqexit - Bits[17:17], RWS_L, default = 1'b0  */
    UINT32 dis_fix_upcfg : 1;
    /* dis_fix_upcfg - Bits[18:18], RWS_L, default = 1'b0  */
    UINT32 dis_check_compl_polact : 1;
    /* dis_check_compl_polact - Bits[19:19], RWS_L, default = 1'b0  */
    UINT32 dis_sym4_reclock_poll_and_cfg : 1;
    /* dis_sym4_reclock_poll_and_cfg - Bits[20:20], RWS_L, default = 1'b0  */
    UINT32 gen_trans_port_stgr : 2;
    /* gen_trans_port_stgr - Bits[22:21], RWS_L, default = 2'b00  */
    UINT32 dis_cfgoff_lanes_sqexit : 1;
    /* dis_cfgoff_lanes_sqexit - Bits[23:23], RWS_L, default = 1'b0  */
    UINT32 dis_ntb_ts2_check : 1;
    /* dis_ntb_ts2_check - Bits[24:24], RWS_L, default = 1'b0  */
    UINT32 dis_rcvd8_ts_check : 1;
    /* dis_rcvd8_ts_check - Bits[25:25], RWS_L, default = 1'b0  */
    UINT32 dis_2ts1lpbk_cmpl_check : 1;
    /* dis_2ts1lpbk_cmpl_check - Bits[26:26], RWS_L, default = 1'b0  */
    UINT32 cfg_lanewait_timer_setting : 2;
    /* cfg_lanewait_timer_setting - Bits[28:27], RWS_L, default = 2'b00  */
    UINT32 en_l0s_tx_drvswctl_sep : 1;
    /* en_l0s_tx_drvswctl_sep - Bits[29:29], RWS_L, default = 1'b0  */
    UINT32 en_l0s_tx_txval_cntr : 1;
    /* en_l0s_tx_txval_cntr - Bits[30:30], RWS_L, default = 1'b0  */
    UINT32 rsvd : 1;
    /* rsvd - Bits[31:31], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DFXCHICKENBIT0_IIO_DFX_STRUCT;
#endif /* ASM_INC */














/* DFXCHICKENBIT1_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x40033B24)                                                  */
/*       IVT_EX (0x40033B24)                                                  */
/*       HSX (0x40033B24)                                                     */
/*       BDX (0x40033B24)                                                     */
/* Register default value:              0x00000041                            */
#define DFXCHICKENBIT1_IIO_DFX_REG 0x12004B24
#ifndef ASM_INC
/* Struct format extracted from XML file BDX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xb24
 */
typedef union {
  struct {
    UINT32 dis_ph3_preset_req : 1;
    /* dis_ph3_preset_req - Bits[0:0], RWS_L, default = 1'b1  */
    UINT32 remote_tx_preset_dfx : 4;
    /* remote_tx_preset_dfx - Bits[4:1], RWS_L, default = 4'b0000  */
    UINT32 en_byp_ph3_with_neq0 : 1;
    /* en_byp_ph3_with_neq0 - Bits[5:5], RWS_L, default = 1'b0  */
    UINT32 dis_mid_max_cal : 1;
    /* dis_mid_max_cal - Bits[6:6], RWS_L, default = 1'b1  */
    UINT32 dis_8b_10b_err_log : 1;
    /* dis_8b_10b_err_log - Bits[7:7], RWS_L, default = 1'b0  */
    UINT32 dis_ntb_ph23_fix : 1;
    /* dis_ntb_ph23_fix - Bits[8:8], RWS_L, default = 1'b0  */
    UINT32 ebdis_lfclk_en_fix : 1;
    /* ebdis_lfclk_en_fix - Bits[9:9], RWS_L, default = 1'b0  */
    UINT32 dis_cfgrec_idle_check : 1;
    /* dis_cfgrec_idle_check - Bits[10:10], RWS_L, default = 1'b0  */
    UINT32 dis_l0s_sqmask : 1;
    /* dis_l0s_sqmask - Bits[11:11], RWS_L, default = 1'b0  */
    UINT32 en_8us_timer_for_all_fub : 1;
    /* en_8us_timer_for_all_fub - Bits[12:12], RWS_L, default = 1'b0  */
    UINT32 dis_pol_invfix : 1;
    /* dis_pol_invfix - Bits[13:13], RWS_L, default = 1'b0  */
    UINT32 dis_gen1_reutfix : 1;
    /* dis_gen1_reutfix - Bits[14:14], RWS_L, default = 1'b0  */
    UINT32 dis_fix4540009 : 1;
    /* dis_fix4540009 - Bits[15:15], RWS_L, default = 1'b0  */
    UINT32 en_txn_eq_bw_only : 1;
    /* en_txn_eq_bw_only - Bits[16:16], RWS_L, default = 1'b0  */
    UINT32 rsvd : 15;
    /* rsvd - Bits[31:17], n/a, default = n/a 
       Padding added by header generation tool.
     */
  } Bits;
  UINT32 Data;
} DFXCHICKENBIT1_IIO_DFX_STRUCT;
#endif /* ASM_INC */


/* XPDFXSPAREREG_IIO_DFX_REG supported on:                                    */
/*       IVT_EP (0x40033B40)                                                  */
/*       IVT_EX (0x40033B40)                                                  */
/*       HSX (0x40033B40)                                                     */
/*       BDX (0x40033B40)                                                     */
/* Register default value on IVT_EP:    0xE7D20002                            */
/* Register default value on IVT_EX:    0xE7D20002                            */
/* Register default value on HSX:       0xC7D20082                            */
/* Register default value on BDX:       0xC7D20182                            */
#define XPDFXSPAREREG_IIO_DFX_REG 0x12004B40


#if defined(HSX_HOST) || defined(BDX_HOST)
#ifndef ASM_INC
/* Struct format extracted from XML file HSX\0.6.3.CFG.xml.
 * generated by critter 06_3_0xb40
 */
typedef union {
  struct {
    UINT32 xpdfxsparereg_en_convert_invcmpl_urcmpl : 1;
    /* xpdfxsparereg_en_convert_invcmpl_urcmpl - Bits[0:0], RW_LV, default = 1'b0 
       if set to '1' will convert CMPLT_INV to CMPLT_MA inbound
     */
    UINT32 xpdfxsparereg_dis_perfboost_pktgen : 1;
    /* xpdfxsparereg_dis_perfboost_pktgen - Bits[1:1], RW_LV, default = 1'b1 
       if reset to '0' increase the perf b.w to 10.6GB/s from 8.0GB/s
     */
    UINT32 rsvd_2 : 3;
    /* rsvd_2 - Bits[4:2], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 en_ib_poison_ma : 1;
    /* en_ib_poison_ma - Bits[5:5], RW_LV, default = 1'b0 
       Set MA hint on all inbound packets with EP=1. Useful for containment of inbound 
       poison writes that trigger LER. 
     */
    UINT32 rsvd_6 : 2;
    UINT32 xpdfxsparereg_bits0 : 8;
    /* xpdfxsparereg_bits0 - Bits[15:8], RW_LV, default = 8'b00000000 (HSX), 8'b00000001 (BDX)  */
    UINT32 xpdfxsparereg_disloweraddr : 1;
    /* xpdfxsparereg_disloweraddr - Bits[16:16], RW_LV, default = 1'b0  */
    UINT32 xpdfxsparereg_discmpl_lowaddr : 1;
    /* xpdfxsparereg_discmpl_lowaddr - Bits[17:17], RW_LV, default = 1'b1  */
    UINT32 disable_msi_gt_1dw : 1;
    /* disable_msi_gt_1dw - Bits[18:18], RW_LV, default = 1'b0 
       If set to 1, Requests with address GT 51 bits and MSI GT 1 DW will not be logged 
       by the PCIE Transaction Layer. 
     */
    UINT32 xpdfxsparereg_en_ecn271_uncerr : 1;
    /* xpdfxsparereg_en_ecn271_uncerr - Bits[19:19], RW_LV, default = 1'b0  */
    UINT32 xpdfxsparereg_en_gosmsg_and_rstwarn_during_abort_inbound : 1;
    /* xpdfxsparereg_en_gosmsg_and_rstwarn_during_abort_inbound - Bits[20:20], RW_LV, default = 1'b1  */
    UINT32 xpdfxsparereg_dis_atomic_poison_check : 1;
    /* xpdfxsparereg_dis_atomic_poison_check - Bits[21:21], RW_LV, default = 1'b0  */
    UINT32 xpdfxsparereg_dis_cfgwr_cmplt_check : 1;
    /* xpdfxsparereg_dis_cfgwr_cmplt_check - Bits[22:22], RW_LV, default = 1'b1  */
    UINT32 xpdfxsparereg_dis_incorrect_cmpl_returned : 1;
    /* xpdfxsparereg_dis_incorrect_cmpl_returned - Bits[23:23], RW_LV, default = 1'b1  */
    UINT32 xpdfxsparereg_dis_incorrect_addr5_2_check : 1;
    /* xpdfxsparereg_dis_incorrect_addr5_2_check - Bits[24:24], RW_LV, default = 1'b1  */
    UINT32 xpdfxsparereg_dis_incorrect_lk_cmpl_check : 1;
    /* xpdfxsparereg_dis_incorrect_lk_cmpl_check - Bits[25:25], RW_LV, default = 1'b1  */
    UINT32 xpdfxsparereg_dis_len_1_0_check : 1;
    /* xpdfxsparereg_dis_len_1_0_check - Bits[26:26], RW_LV, default = 1'b1 
       if set to '0' will compare the LEN[1:0] of the received CMPL dev[4:3] with 
       LEN[1:0] 
     */
    UINT32 xpdfxsparereg_en_x16_ler_check : 1;
    /* xpdfxsparereg_en_x16_ler_check - Bits[27:27], RW_LV, default = 1'b0  */
    UINT32 xpdfxsparereg_en_x16_ler_dump : 1;
    /* xpdfxsparereg_en_x16_ler_dump - Bits[28:28], RW_LV, default = 1'b0  */
    UINT32 rsvd_29 : 1;
    /* rsvd_29 - Bits[29:29], n/a, default = n/a 
       Padding added by header generation tool.
     */
    UINT32 enable_at_switch_swizzle : 1;
    /* enable_at_switch_swizzle - Bits[30:30], RW_LV, default = 1'b1 
       If set to 1, the AT field in the switch header will be zero for ACS completer 
       abort cases. 
     */
    UINT32 rsvd_31 : 1;
  } Bits;
  UINT32 Data;
} XPDFXSPAREREG_IIO_DFX_HSX_BDX_STRUCT;
#endif /* ASM_INC */
#endif /* (HSX_HOST) || defined(BDX_HOST) */






/* DIO0TGTRNG_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x40033280)                                                  */
/*       IVT_EX (0x40033280)                                                  */
/* Register default value:              0x18000000                            */
#define DIO0TGTRNG_IIO_DFX_REG 0x12004280



/* DIOTGTDELS_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x40033284)                                                  */
/*       IVT_EX (0x40033284)                                                  */
/* Register default value:              0x00000000                            */
#define DIOTGTDELS_IIO_DFX_REG 0x12004284



/* DIOIBDELS_IIO_DFX_REG supported on:                                        */
/*       IVT_EP (0x40033290)                                                  */
/*       IVT_EX (0x40033290)                                                  */
/* Register default value:              0x00000000                            */
#define DIOIBDELS_IIO_DFX_REG 0x12004290



/* DIOTODELS0_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x400332A8)                                                  */
/*       IVT_EX (0x400332A8)                                                  */
/* Register default value:              0x00000000                            */
#define DIOTODELS0_IIO_DFX_REG 0x120042A8



/* DIOTODELS1_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x400332AC)                                                  */
/*       IVT_EX (0x400332AC)                                                  */
/* Register default value:              0x00000000                            */
#define DIOTODELS1_IIO_DFX_REG 0x120042AC



/* RX_CTLE_PEAK_GEN1_IIO_DFX_REG supported on:                                */
/*       IVT_EP (0x40033690)                                                  */
/*       IVT_EX (0x40033690)                                                  */
/* Register default value:              0x11111111                            */
#define RX_CTLE_PEAK_GEN1_IIO_DFX_REG 0x12004690



/* RX_CTLE_PEAK_GEN2_IIO_DFX_REG supported on:                                */
/*       IVT_EP (0x40033694)                                                  */
/*       IVT_EX (0x40033694)                                                  */
/* Register default value:              0x88888888                            */
#define RX_CTLE_PEAK_GEN2_IIO_DFX_REG 0x12004694



/* RX_CTLE_PEAK_GEN3_IIO_DFX_REG supported on:                                */
/*       IVT_EP (0x40033698)                                                  */
/*       IVT_EX (0x40033698)                                                  */
/* Register default value:              0xDDDDDDDD                            */
#define RX_CTLE_PEAK_GEN3_IIO_DFX_REG 0x12004698



/* PIVCM1SEL_IIO_DFX_REG supported on:                                        */
/*       IVT_EP (0x40033A00)                                                  */
/*       IVT_EX (0x40033A00)                                                  */
/* Register default value:              0x00000000                            */
#define PIVCM1SEL_IIO_DFX_REG 0x12004A00



/* PIVCM2SEL_IIO_DFX_REG supported on:                                        */
/*       IVT_EP (0x40033A04)                                                  */
/*       IVT_EX (0x40033A04)                                                  */
/* Register default value:              0x00000000                            */
#define PIVCM2SEL_IIO_DFX_REG 0x12004A04



/* RT_BIN_OFFSET_RX_IIO_DFX_REG supported on:                                 */
/*       IVT_EP (0x40033A08)                                                  */
/*       IVT_EX (0x40033A08)                                                  */
/* Register default value:              0x00000000                            */
#define RT_BIN_OFFSET_RX_IIO_DFX_REG 0x12004A08



/* RT_BIN_OFFSET_TX_IIO_DFX_REG supported on:                                 */
/*       IVT_EP (0x40033A10)                                                  */
/*       IVT_EX (0x40033A10)                                                  */
/* Register default value:              0x00000000                            */
#define RT_BIN_OFFSET_TX_IIO_DFX_REG 0x12004A10



/* RT_MODE_SEL_RX_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x40033A18)                                                  */
/*       IVT_EX (0x40033A18)                                                  */
/* Register default value:              0x00000000                            */
#define RT_MODE_SEL_RX_IIO_DFX_REG 0x12004A18



/* RT_MODE_SEL_TX_IIO_DFX_REG supported on:                                   */
/*       IVT_EP (0x40033A1C)                                                  */
/*       IVT_EX (0x40033A1C)                                                  */
/* Register default value:              0x00000000                            */
#define RT_MODE_SEL_TX_IIO_DFX_REG 0x12004A1C



/* TX_SKEW_CTRL_IIO_DFX_REG supported on:                                     */
/*       IVT_EP (0x40033A68)                                                  */
/*       IVT_EX (0x40033A68)                                                  */
/* Register default value:              0x000000FF                            */
#define TX_SKEW_CTRL_IIO_DFX_REG 0x12004A68



/* XPPRIVCNEW_IIO_DFX_REG supported on:                                       */
/*       IVT_EP (0x40033B18)                                                  */
/*       IVT_EX (0x40033B18)                                                  */
/* Register default value:              0x00000001                            */
#define XPPRIVCNEW_IIO_DFX_REG 0x12004B18



#endif /* IIO_DFX_h */
